rfndmw
Member level 4
hi..I have designed a source fed FET mixer...I am aware of the biasing region for this type of mixers...when I tested the designed mixer however, I found tht it gave lowest conversion loss at drain voltage almost 0 i.e. at 0.1 V. but I had designed the mixer for an operating point of drain voltage at about 2 V. the reuslts are really bad and I believe its because the transistor is nt being biased properly..am I right or could smethng else be the reason for the drain voltage shift I see. could sme1 plz tell me how to calculate the correct values of the shunt gate resistor I use to supply to gate voltage(and fr stabilizing) and the drain resistor via which I apply the drain voltage for this kind of mixer...any help would be appreciated...thnx