Mixed verilog and vhdl code

[altair_06]

Hi,

Can there be mixed verilog and vhdl code? and if possible would the compiler support it. If there is a possiblity can anyone give me a sample code.

 

[chviswanadh]

I dont think you can do both in the same design. but there are simulators(most of them) which support both types

 

[zeeshanzia84]

I have written some modules in VHDL and their testbenches were written in Verilog..and my simulator (ModelSim) supports it well.

I think that you CAN have different modules written in Verilog and VHDL in the same design(kept in separate files)..they simply interact through their ports...

However, ofcourse you can't mix VHDL and Verilog in the same module...like maybe C and inline Assembly.....

 

[jjww110]

modelsim support mix language well , nc is a bit worse!!

 

[aji_vlsi]

Hi,

Can there be mixed verilog and vhdl code? and if possible would the compiler support it. If there is a possiblity can anyone give me a sample code.

Yes it works as long as they are in separate files and model different modules (of same design). I can't imagine why would you need within SAME module 2 languages, anyway that's not what you are asking for anyway.

I've used it with MTI, VCSMX and NC - all work fine, MTI was a smooth flow compared to the rest, but recently NC & VCSMX have caught up as well. Especially for SystemVerilog & VHDL VCSMX and MTI do a good job, not sure what NC does there.

HTH
Ajeetha, CVC
Contemporary Verification Consultants Pvt Ltd. h**p://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 h**p://www.systemverilog.us/
* SystemVerilog Assertions Handbook
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