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mixed-language digital simulator usage

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wenchao

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mixed language digital simulations

Dear All,

I am using ModelSim for Verilog and VHDL mixed-language digital simulation. Does anybody know about other digital simulator for VHDL and Verilog mixed-language simulator? Can anybody share me with his experience for using them? thanks!
 

cganeshprabhu

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mixed language simulation nc

Hi,

There is also a simulator from Synopsis called as VCS-MX where VCS is for verilog and Scirocco-MX is for VHDL. U can also do mixed simulation using this Simulator.

I basically deal with debuggers for design. I too provide the linking for my debugger with VCS-MX for mixed Design.

Cadence also gives a simulator for mixed design, where u need to do seperately for Verilog modules and vhdl entities in the run.f file and can get the output for mixed design.

Regards,
GP
 

amarnath

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vcs simulator on mixed hdl

aldec active hdl is a very good mixed isgnal simulator comparable with modelsim..in terms of feaatures and speed..i think active hdl is more easier to use for beginners...u can request an evaluation version..from aldec at...

www.aldec.com
 

CatKing

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for mixed hdl sim, modelsim takes the most market share, but ldv or vcs_mx also can do the job.
 

z81203

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aldec riviera
cadence nc-sim
synopsys vcs-mx
mentor modelsim
 

elektor

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Hi,
Aldec Active HDL is most userfriendly but no so good ( lot of bugs)
Modelsim is better , but NC-Sim is the best. It can find bug in core even if Modelsim saying "good ;)...
Its's all mixed-language of course...

Regards
Elektor
 

wenchao

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elektor said:
Hi,
Aldec Active HDL is most userfriendly but no so good ( lot of bugs)
Modelsim is better , but NC-Sim is the best. It can find bug in core even if Modelsim saying "good ;)...
Its's all mixed-language of course...

Regards
Elektor

Dear Elektor,

Can you give me more about using the NC-Sim for mix language simulation. I try to use NC-Sim for mix language simualtion and with Debussy for wave form viewer and source code tracing, debugging. I can link and elaborate the design but simulation failed. The NC-Sim complain wiht run-time error and no more. It seems that the Novas Debussy caused the problem. Do I have to compile (link and elaborate) the Verilog and VHDL modules saperately? How to link with Debussy? Thanks!

Regards

Wenchao
 

eda_wiz

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elektor said:
Hi,
Aldec Active HDL is most userfriendly but no so good ( lot of bugs)
Modelsim is better , but NC-Sim is the best. It can find bug in core even if Modelsim saying "good ;)...
Its's all mixed-language of course...

Regards
Elektor

I have used Active HDl many times... havent come across any bugs till now .. infact i had many crashes with modelsim simultor :)
 

W

wang1

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Hi,

modelsim have single kernal run mixed-hdl simulate, so the speed will

better. :)
 

anjf

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whizkid said:
I have used Active HDl many times... havent come across any bugs till now .. infact i had many crashes with modelsim simultor :)


Modelsim is much faster than Active HDL, especially when the post simulation with the .sdf file.
 

kermit

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I think modelsim is more friendly than nc-sim and vcs-mx!
but I think vcs-mx is the fastest simulator around the world.because it is compiled the code then run.
 

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