Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Minstep Violation in SOC encounter

Status
Not open for further replies.

a_mythpi

Junior Member level 1
Joined
Mar 17, 2013
Messages
16
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,410
Hello.

I get a certain "Minstep Violation" when i run verify geometry for my design (violation is in the full custom cell I have designed) with same cell violations disallowed. Can anyone please explain me what exactly is this violation and how it can be fixed?

Cheers

Amith
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top