biju4u90
Full Member level 3
What are the minimum required constraints to be given while synthesising a design?
1. clock period
2. input delay
3. output delay
4. clock uncertainity
5. clock latency
6. set load
Other than the constraints listed above, what are the basic constraints required?
1. clock period
2. input delay
3. output delay
4. clock uncertainity
5. clock latency
6. set load
Other than the constraints listed above, what are the basic constraints required?