In the layout, the X snap spacing and Y snap spacing can be setted.
I had setted these spacings as 0.005 when I drawed the layout, but afterwards, I found there seems to be a minimum gird setting defined by the technology. This minimum grid is probably 0.05 um in the technology.
SO are there any problems if my spacings settings is too small, will it influence the chip fabrication?
yes there is. if your'e using a tool that has a snap to grid function. it helps. just make sure that your'e using a process that also uses 1 type of grid.
first never go beyond the minimum precision. this will give you OFF GRID errors. believe me this is the WORST DRC error. you have to do your layout again at most if you encounter this error. if a spacing requires 0.15 um put your accuracy to 0.1, then just go for 0.2 um spacing. well if you really want to save space, then you can go down to 0.01 accuracy but i don't think it will really give you a lot of saved space especially when your layout is just a small one.
are you using virtuoso? you can go the options menu then click the display pull down menu. you can see the x and y snap spacing.
The minimum grid is specified by the foundry.
During fabrication, the fabrication tip moves only on the grid. so all the off-grid points will not be formed properly. In some cases the artifacts or some other minor shapes can be waived for off-grid. devices should not be offgrid.
From my own experience, after my DRC execution many offgrid errors appeared on the drc report. I think they will not fabricate a layout w/ drc errors unless those are proven psuedo errors.