minimum component spacing in the automatic pick-and-place

[jayleung]

Hi, everyone. I have a question about the minimum component spacing in the automatic pick-and-place assemble process.

Let's say that I design a complete circuit with all kinds of components, with QFN, TSSOP, SOIC ics, and 0402,0603,0805 capacitors and resistors. So how close those components can be in the automatic pick-and-place assemble process? For example, for a 4mmx4mm QFN (160x160mil^2) package, can I place a 0402 (40x20mil^2) decoupling capacitor 20mil away from the IC? Or 40mil?

Thanks.

 

[ftsolutions]

Re: minimum component spacing in the automatic pick-and-plac

It depends on the capabilities of the manufacturing facility that will build the board. That said, even if it is within the capabilities, it may not result in something that can be easily ported to other mfgr locations, or be a design which provides acceptable manufacturing yield if the placements and soldermask, vias, and apertures are prone to solder bridging, solder thieving, or other flow problems. Thickness of the PCB, copper weight, and technology (very fine pitch SMT, proximity to BGA, heavy thermal areas, etc. also can affect placement.

Suggest that you look for some IPC-6xx manufacturing/quality standards and/or talk to someone in pcb manufacturing/assembly for a list of their typical criteria for evaluating designs. There is a science to "design for manufacturability", and if you're planning to build thousands or millions of something, you gotta get it right or the quality issues will burn you.

 

[kvmanikandan]

hi,
basically the common placement distance one component outline(component body) to another component is 1mm its enough.

this dim. from ipc 2221