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MIN Tran Violation in the design

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spgite

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Yes, I am facing min tran violation at fast corners. Limit set is 50ps and actual tran is 25ps.
I am trying to understand why min tran is needed. What if I reduce my tran limit to less than 25ps (to remove the violation), how it will affect my design.
 

dick_freebird

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Transient convergence, any difficulties in following a
fast edge will make the timestep downrange and if the
simulator has "gotten out over its skis" (accepted a
large timestep solution-point as valid, and then it
discovers it missed something) it can't downrange far
enough to reacquire acceptable tolerance and instead
tries until it hits the min timestep limit.

You can reduce that limit but when you get to under
(say) 1/10 of a natural logic gate risetime, and still
are failing, you need to look at different numerical solution
method options, adding trivial capacitors to unloaded
nodes (or cmin param) and so on to make the transient
goings-on less unrealistically abrupt.

Affects the design not at all - just your accuracy at
modeling its behavior.
 

spgite

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Thank you for reply...

So what I understood from your reply (Sorry...I am not aware of Simulation methdology your are talking about)

We cant reduce the limit directly...There must be a minimum transition time on a signal...or else the logical gate may not capture it...
 

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