Jul 23, 2021 #1 S stanford Full Member level 2 Joined Feb 16, 2014 Messages 132 Helped 4 Reputation 8 Reaction score 6 Trophy points 1,298 Activity points 2,223 Why do we have a check for min skew? What does this help avoid? Thanks!
Jul 23, 2021 #2 O oratie Full Member level 6 Joined Jan 10, 2007 Messages 381 Helped 178 Reputation 354 Reaction score 182 Trophy points 1,323 Activity points 4,716 For example: if you have zero clock skew, all flops will switch at the same time. It will cause big IR-drop. Upvote 0 Downvote
For example: if you have zero clock skew, all flops will switch at the same time. It will cause big IR-drop.
Jul 23, 2021 #3 S stanford Full Member level 2 Joined Feb 16, 2014 Messages 132 Helped 4 Reputation 8 Reaction score 6 Trophy points 1,298 Activity points 2,223 ah thanks, any other reasons? Upvote 0 Downvote
Jul 23, 2021 #4 O oratie Full Member level 6 Joined Jan 10, 2007 Messages 381 Helped 178 Reputation 354 Reaction score 182 Trophy points 1,323 Activity points 4,716 Another example is "Source-Synchronous clocking". Clock signal delay can not be less than data signal delay. Upvote 0 Downvote
Another example is "Source-Synchronous clocking". Clock signal delay can not be less than data signal delay.
Nov 19, 2021 #5 S stanford Full Member level 2 Joined Feb 16, 2014 Messages 132 Helped 4 Reputation 8 Reaction score 6 Trophy points 1,298 Activity points 2,223 oratie said: Another example is "Source-Synchronous clocking". Clock signal delay can not be less than data signal delay. Click to expand... Why do you want delay_clk > delay_data in Source-Synchronous path? Wouldn't this make the hold violation worse? Upvote 0 Downvote
oratie said: Another example is "Source-Synchronous clocking". Clock signal delay can not be less than data signal delay. Click to expand... Why do you want delay_clk > delay_data in Source-Synchronous path? Wouldn't this make the hold violation worse?