MIMCAP density rule (urgent) Should I put in dummies?

[sharkies]

Hey guys,
I have couple MIMcap arrays for my design.
I have very little routing going through the MIMcap array and if I run chip-level DRC, it gives me density errors.
How do people get away with this error? Do you waive them?
The PDK shows that nothing should be routed underneath the mimcap.
Also, if I decide to put in dummies using the script, dummies will be all over the place.
If I put in dummies under each unit MIMCAP manually to maintain symmetry, I still think this will affect linearity.
The errors that pop-up are local density rules for M1~M6.
There's also a PO density rule under each MIMCAP as well... I need to put in PO manually to clean this just like the metal density rules. Can I just get the PO and the metals waived?
Does anybody have experience with this(I understand this is process dependent)? or a general guidline?


any clue? I'm kinda reluctant to put in anything below the MIMcap structure.

 

[erikl]

If I put in dummies under each unit MIMCAP manually to maintain symmetry, I still think this will affect linearity. I'm kinda reluctant to put in anything below the MIMcap structure.

If you put a full, overlapping screen (or a regular grid, if a full screen also violates DRC rules) below the MIMCAPs, this shouldn't affect linearity. Connect it to GND - or leave it floating, if you need low bottom plate parasitics.

There's also a PO density rule under each MIMCAP as well... I need to put in PO manually to clean this just like the metal density rules. Can I just get the PO and the metals waived?

No, you won't get any density rule violations waived - at least not for a multi-client wafer, 'cause such violations could jeopardize the yield of the whole wafer.
For the poly layer, you could use the same type of screen as for the metal layer(s) beyond.

 

[dick_freebird]

The MIM caps I use have built into the PCell, little tabs.
That means a ring of non-MIM overhead, where stuff
could be put.

You might rework a MIMCAP unit to incorporate density
features outboard of the plates. Or, you might be on a
flow that allows other layers under MIM, in which case
you can just put junk under the bottom plate to fill.
Just make it so every unit is the same and the matching
ought not to be compromised.

 

[sharkies]

Thanks,, both of you have recommended to put regular metals (1~6 to path density) underneath the unit MIMCAP
this is kinda scary to me I just feel like it's gonna drop the linearity... argh..
I guess I gotta decide .. hm..

 

[erikl]

I just feel like it's gonna drop the linearity... argh..

Why should an array-overlapping regular pattern (with small dimensions compared to your MIMCAP unit) affect the linearity of the array?

 

[sharkies]

Thanks for keeping up erikl.

The PDK mentions not to route anything under the mimcap structure.
I think(?) this may be due to the fact that the cell models substrate parasitic cap with the assumption that there's no metal underneath.
Nevertheless, since the PDK says not to do it, it makes me hesitate.
MIMcap has great linearity (characterized without undermetals) and I feel like I shouldn't be messing around with the structure.


Have you personally built regular patterns underneath mimcaps?
I need a good 12bit cap linearity here. Current mimcap unit size is 60fF. and I have single row, single columng dummy caps along the edges

argh... late rush adrenaline...

 

[erikl]

The PDK mentions not to route anything under the mimcap structure.
I think(?) this may be due to the fact that the cell models substrate parasitic cap with the assumption that there's no metal underneath.
Nevertheless, since the PDK says not to do it, it makes me hesitate.
MIMcap has great linearity (characterized without undermetals) and I feel like I shouldn't be messing around with the structure.

Understandable. If you got your PDK from the same foundry which defines the density design rules, there's certainly an act of caprice. I think you should ask them how to proceed.

Have you personally built regular patterns underneath mimcaps?
I need a good 12bit cap linearity here. Current mimcap unit size is 60fF. and I have single row, single columng dummy caps along the edges

We didn't have this density problem, so: no, nothing underneath. It also was a 12bit ADC, presumably different architecture, 180nm process, mimcap unit size 125fF. Layout changes until total parasitic cap value differences of the important nodes ≦ 1% in the end succeeded in 11bit ENOB. In order to save some space, instead of outside dummies we decided on a specially formed grounded guardRing on the 2 topmost metal layers, s. this PDF: View attachment adc_caparray-guardRing.pdf