using xilinx netlist for altera
maestor
I have asked Xilinx, they advice to use AHDL2HDL utility, but it does not help me to convert whole project.
r_e_m_y
Yesterday evening i arrived at a conclusion that this is only way to make a migration. I think the scenario should be:
- Load the project in Quartus and compile it;
- Archive compiled project and then extract the Archive in other directory. This directory will contain all files of the project (include LPMs);
- For every graphic file in this directory: Open *.bdf -> Create project -> Create HDL design file from curreng graphic;
- For Verilog files - nothing to do;
- For LPMs files - rewrite them in Verilog manually. 8O
It would be good, if somebody could advise me a library with Altera's LPMs converted to Verilog or VHDL.
- Finally i build a directory contains only Verilog files, define the top of hierarchy and compile it in Xilinx ISE. ISE should rebuild all project structure automaticaly.
Thanks for advice!