Migrate "generate statements" from DC to RTLCompil

[kamalkundu]

Hello,

We are migrating from DC to RTL Compiler(Cadence). Design engineers have used generate statements exhaustively which were easily understood by DC. But I am wondering how can we utilize same verilog code (with generate statements) in RTL Compiler.
code example:
=============================
generate if (xyz == 1'b1) begin :
module M( .A(A), .B(B)) ;
end
endgenerate

==============================

All ideas/suggestion are welcome!

Thanks

 

[aravind]

Re: Migrate "generate statements" from DC to RTLCo

generate statement is supported in RC. but i never seen generate statement before module statement.. You can always file a SR to get a solution immediately..