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MIG, Place and Route timing constraint problem

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hastidot

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Hi all
I'm using MIG for DDR2 controlling on virtex5.
The oscillator on the board works with 50 Mhz. But since the MIG does not accept frequencies lower than 125Mhz, I generated the design for 125 Mhz. I used a DCM2PLL module . First in DCM, a 125Mhz clock is generated from 50 Mhz, then in PLL, he clk0, clk90, clkdiv0 and clk200 (125Mhz, 62.5 Mhz and 200 Mhz).are genarted. According to my simulation results, are the clocks have been generated correctly.
But in the place and route stage, I have one timing constrant error.
Some additional frequencies (i.e 500Mhz) appear in the constraints for some modules. I don't know what is the problem with my clocking scheme.


Timing report in Place & Route stage:


Slack (setup path): -0.672ns (requirement - (data path - clock path skew + uncertainty))
Source: u_mig/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF)
Destination: u_mig/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_wr/.gen_wdf[1].u_wdf (RAM)
Requirement: 2.000ns
Data Path Delay: 2.248ns (Levels of Logic = 1)
Clock Path Skew: -0.215ns (4.423 - 4.638)
Source Clock: clkdiv0_bufg rising at 0.000ns
Destination Clock: clk90_bufg rising at 2.000ns
Clock Uncertainty: 0.209ns


The Requirement is 2ns which is equal to 500 Mhz, the frequency which I did not generate at all in my design. :sad:
 

did you make sure to use the multi-path constraints in the UCF as well? the path shown is from the divided clock to the 90deg clock. this is 1/4th as long as the 8ns clock, or 2ns.
 

Dear Permute

Thank you for your reply.
To be honest I'm not familiar with the UCF constraint. In the UCF which has been generated in the example_design file, there are some constraint instructions which I don't know what they mean. I eliminated them in the UCF which is added in my design. Please guide me whether I should use them in my design or not:
The following are the generated UCF constraints:


############################################################################
# Clock constraints #
############################################################################

NET "clk0" TNM_NET = "SYS_clk0";
TIMESPEC "TS_SYS_clk0" = PERIOD "SYS_clk0" 8 ns HIGH 50 %;

NET "clk90" TNM_NET = "SYS_clk90";
TIMESPEC "TS_SYS_clk90" = PERIOD "SYS_clk90" "TS_SYS_clk0" PHASE 2 ns HIGH 50 %;

NET "clkdiv0" TNM_NET = "SYS_clkdiv0";
TIMESPEC "TS_SYS_clkdiv0" = PERIOD "SYS_clkdiv0" "TS_SYS_clk0" * 2 HIGH 50 %;

NET "clk200" TNM_NET = "SYS_clk200";
TIMESPEC "TS_SYS_clk200" = PERIOD "SYS_clk200" 5 ns HIGH 50 %;

########################################################################

###############################################################################
# Define multicycle paths - these paths may take longer because additional
# time allowed for logic to settle in calibration/initialization FSM
###############################################################################

# MIG 2.1: Eliminate Timegroup definitions for CLK0, and CLK90. Instead trace
# multicycle paths from originating flip-flop to ANY destination
# flip-flop (or in some cases, it can also be a BRAM)
# MUX Select for either rising/falling CLK0 for 2nd stage read capture
INST "*/u_phy_calib/gen_rd_data_sel*.u_ff_rd_data_sel" TNM = "TNM_RD_DATA_SEL";
TIMESPEC "TS_MC_RD_DATA_SEL" = FROM "TNM_RD_DATA_SEL" TO FFS
"TS_SYS_clk0" * 4;
# MUX select for read data - optional delay on data to account for byte skews
INST "*/u_usr_rd/gen_rden_sel_mux*.u_ff_rden_sel_mux" TNM = "TNM_RDEN_SEL_MUX";
TIMESPEC "TS_MC_RDEN_SEL_MUX" = FROM "TNM_RDEN_SEL_MUX" TO FFS
"TS_SYS_clk0" * 4;
# Calibration/Initialization complete status flag (for PHY logic only) - can
# be used to drive both flip-flops and BRAMs
INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
"TS_SYS_clk0" * 4;
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_90" = FROM "TNM_PHY_INIT_DATA_SEL" TO RAMS
"TS_SYS_clk0" * 4;
# Select (address) bits for SRL32 shift registers used in stage3/stage4
# calibration
INST "*/u_phy_calib/gen_gate_dly*.u_ff_gate_dly" TNM = "TNM_GATE_DLY";
TIMESPEC "TS_MC_GATE_DLY" = FROM "TNM_GATE_DLY" TO FFS "TS_SYS_clk0" * 4;

INST "*/u_phy_calib/gen_rden_dly*.u_ff_rden_dly" TNM = "TNM_RDEN_DLY";
TIMESPEC "TS_MC_RDEN_DLY" = FROM "TNM_RDEN_DLY" TO FFS "TS_SYS_clk0" * 4;

INST "*/u_phy_calib/gen_cal_rden_dly*.u_ff_cal_rden_dly"
TNM = "TNM_CAL_RDEN_DLY";
TIMESPEC "TS_MC_CAL_RDEN_DLY" = FROM "TNM_CAL_RDEN_DLY" TO FFS
"TS_SYS_clk0" * 4;
###############################################################################
# DQS Read Post amble Glitch Squelch circuit related constraints
###############################################################################


###############################################################################
# LOC placement of DQS-squelch related IDDR and IDELAY elements
# Each circuit can be located at any of the following locations:
# 1. Unused "N"-side of DQS differential pair I/O
# 2. DM data mask (output only, input side is free for use)
# 3. Any output-only site
###############################################################################

INST "*/gen_dqs[0].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y302";
INST "*/gen_dqs[0].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y302";
INST "*/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y300";
INST "*/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y300";
INST "*/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y298";
INST "*/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y298";
INST "*/gen_dqs[3].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y262";
INST "*/gen_dqs[3].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y262";
INST "*/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y260";
INST "*/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y260";
INST "*/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y258";
INST "*/gen_dqs[5].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y258";
INST "*/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y222";
INST "*/gen_dqs[6].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y222";
INST "*/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce" LOC = "ILOGIC_X0Y220";
INST "*/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce" LOC = "IODELAY_X0Y220";

###############################################################################
# LOC and timing constraints for flop driving DQS CE enable signal
# from fabric logic. Even though the absolute delay on this path is
# calibrated out (when synchronizing this output to DQS), the delay
# should still be kept as low as possible to reduce post-calibration
# voltage/temp variations - these are roughly proportional to the
# absolute delay of the path
###############################################################################

INST "*/u_phy_calib/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X0Y151;
INST "*/u_phy_calib/gen_gate[1].u_en_dqs_ff" LOC = SLICE_X0Y150;
INST "*/u_phy_calib/gen_gate[2].u_en_dqs_ff" LOC = SLICE_X0Y149;
INST "*/u_phy_calib/gen_gate[3].u_en_dqs_ff" LOC = SLICE_X0Y131;
INST "*/u_phy_calib/gen_gate[4].u_en_dqs_ff" LOC = SLICE_X0Y130;
INST "*/u_phy_calib/gen_gate[5].u_en_dqs_ff" LOC = SLICE_X0Y129;
INST "*/u_phy_calib/gen_gate[6].u_en_dqs_ff" LOC = SLICE_X0Y111;
INST "*/u_phy_calib/gen_gate[7].u_en_dqs_ff" LOC = SLICE_X0Y110;

# Control for DQS gate - from fabric flop. Prevent "runaway" delay -
# two parts to this path: (1) from fabric flop to IDELAY, (2) from
# IDELAY to asynchronous reset of IDDR that drives the DQ CE's
# This can be relaxed by the user for lower frequencies:
# 300MHz = 850ps, 267MHz = 900ps. At 200MHz = 950ps.
# In general PAR should be able to route this
# within 900ps over all speed grades.
NET "*/u_phy_io/en_dqs*" MAXDELAY = 600 ps;
NET "*/u_phy_io/gen_dqs*.u_iob_dqs/en_dqs_sync" MAXDELAY = 800 ps;

###############################################################################
# "Half-cycle" path constraint from IOB flip-flop to CE pin for all DQ IDDR's
# for DQS Read Post amble Glitch Squelch circuit
###############################################################################

# Max delay from output of IOB flip-flop to CE input of DQ IDDRs =
# tRPST + some slack where slack account for rise-time of DQS on board.
# For now assume slack = 0.400ns (based on initial SPICE simulations,
# assumes use of ODT), so time = 0.4*Tcyc + 0.40ns = 1.6ns @333MHz
INST "*/gen_dqs[*].u_iob_dqs/u_iddr_dq_ce" TNM = "TNM_DQ_CE_IDDR";
INST "*/gen_dq[*].u_iob_dq/gen_stg2_*.u_iddr_dq" TNM = "TNM_DQS_FLOPS";
TIMESPEC "TS_DQ_CE" = FROM "TNM_DQ_CE_IDDR" TO "TNM_DQS_FLOPS" 3.6 ns;


I'm some how puzzled. I'm using MIG 3.1, but somewhere in the text I can see MIG 2.1 (????). Also there are some LOC and timing constraints for flop driving DQS and else, which I can not see these locations in my boards datasheet. (i.e for LOC = SLICE_X0Y129, SLICE_X0Y129 is not defined in the schematic !!!!)
Thank you in advance
 

pretty much everything is required. Some of the comments don't get updated, so there will be some older versions of MIG called out. The entire system solves an IO problem in a fairly elaborate manner. You need to use the UCF that was generated for your specific FPGA. The LOC's are all internal nodes in the FPGA. The addressing is based on the size of the FPGA, so it will change from part to part. The HDL also has two parameter/generic that are associated. These define which half of the FPGA the IO is in, as well as if the IO is in a P/N location.

INST "*/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_DATA_SEL";
TIMESPEC "TS_MC_PHY_INIT_DATA_SEL_0" = FROM "TNM_PHY_INIT_DATA_SEL" TO FFS
"TS_SYS_clk0" * 4;

as you can see, the 2ns net that failed actually has a 32ns requirement.
 
I C. you'r right. But I have another question. In order to use these constraints , first I have to use clocking constraints (which are indicated at the first). But the only clock which is defined as a NET in my UCF file, is "sysclk", which is my system clock (equal to 50Mhz) and all the other clocks are generated in a PLL using sysclk. These clocks are defined as "wire" in my top module. But as it can be seen in UCF file, all the four clocks (clk0, clk90, clkdiv0 & clk200) are treated as NETs. Accordingly, how can I use these constraints ?
# Clock constraints #
############################################################################

NET "clk0" TNM_NET = "SYS_clk0";
TIMESPEC "TS_SYS_clk0" = PERIOD "SYS_clk0" 8 ns HIGH 50 %;

NET "clk90" TNM_NET = "SYS_clk90";
TIMESPEC "TS_SYS_clk90" = PERIOD "SYS_clk90" "TS_SYS_clk0" PHASE 2 ns HIGH 50 %;

NET "clkdiv0" TNM_NET = "SYS_clkdiv0";
TIMESPEC "TS_SYS_clkdiv0" = PERIOD "SYS_clkdiv0" "TS_SYS_clk0" * 2 HIGH 50 %;

NET "clk200" TNM_NET = "SYS_clk200";
TIMESPEC "TS_SYS_clk200" = PERIOD "SYS_clk200" 5 ns HIGH 50 %;

########################################################################

I checked the datasheet of the board, there are no pins which I can assign these clocks to! I'm somehow puzzled with using these constraints!!!!

---------- Post added at 12:06 ---------- Previous post was at 10:07 ----------

According to the cgd.pdf, I first implemeted timing constraint on "sysclk" and then used special commands to implement constraints on PLL output clocks (page 59).
Then I used constraints which were indicated in UCF file in my design. Now, as I implement my design on the board, in the summary it is indicated that "All timing constraints met" with no errors.

Thank you in advance. you helped me so much handling timing problems :wink:
 

I C. you'r right. But I have another question. In order to use these constraints , first I have to use clocking constraints (which are indicated at the first). But the only clock which is defined as a NET in my UCF file, is "sysclk", which is my system clock (equal to 50Mhz) and all the other clocks are generated in a PLL using sysclk. These clocks are defined as "wire" in my top module. But as it can be seen in UCF file, all the four clocks (clk0, clk90, clkdiv0 & clk200) are treated as NETs. Accordingly, how can I use these constraints ?
# Clock constraints #
############################################################################

NET "clk0" TNM_NET = "SYS_clk0";
TIMESPEC "TS_SYS_clk0" = PERIOD "SYS_clk0" 8 ns HIGH 50 %;

NET "clk90" TNM_NET = "SYS_clk90";
TIMESPEC "TS_SYS_clk90" = PERIOD "SYS_clk90" "TS_SYS_clk0" PHASE 2 ns HIGH 50 %;

NET "clkdiv0" TNM_NET = "SYS_clkdiv0";
TIMESPEC "TS_SYS_clkdiv0" = PERIOD "SYS_clkdiv0" "TS_SYS_clk0" * 2 HIGH 50 %;

NET "clk200" TNM_NET = "SYS_clk200";
TIMESPEC "TS_SYS_clk200" = PERIOD "SYS_clk200" 5 ns HIGH 50 %;

########################################################################

I checked the datasheet of the board, there are no pins which I can assign these clocks to! I'm somehow puzzled with using these constraints!!!!

---------- Post added at 12:06 ---------- Previous post was at 10:07 ----------

According to the cgd.pdf, I first implemeted timing constraint on "sysclk" and then used special commands to implement constraints on PLL output clocks (page 59).
Then I used constraints which were indicated in UCF file in my design. Now, as I implement my design on the board, in the summary it is indicated that "All timing constraints met" with no errors.

Thank you in advance. you helped me so much handling timing problems :wink:

I am having similar issues. What were the special commands you used?
Also what are the final constraints you used in UCF afterwards?
 

These are my clock constraints which seem to work fine:


NET "ddr_src_clk0" TNM_NET = "tnm_ddr_src_clk0_bufg";
TIMESPEC "TS_ddr_src_clk0_bufg" = PERIOD "tnm_ddr_src_clk0_bufg" 6 ns HIGH 50 %;

NET "ddr_src_clk0" TNM = FFS "TNM_DDR_SRC_CLK0";

NET "ddr_src_clk90" TNM_NET = "tnm_ddr_src_clk90_bufg";
TIMESPEC "TS_ddr_src_clk90_bufg" = PERIOD "tnm_ddr_src_clk90_bufg" TS_ddr_src_clk0_bufg PHASE + 1.5 ns;

NET "ddr_src_clk90" TNM = FFS "TNM_DDR_SRC_CLK90";

NET "ddr_src_clkdiv0" TNM_NET = "tnm_ddr_src_clkdiv0_bufg";
TIMESPEC "TS_ddr_src_clkdiv0_bufg" = PERIOD "tnm_ddr_src_clkdiv0_bufg" 12 ns HIGH 50 %;
 

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