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MIG output to instaniate in my design

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Advanced Member level 4
Aug 15, 2010
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I have created a controller for DDR3 with the MIG. MIG output folders are example_design and user_design. according to MIG report :
- example_design:
This folder includes the design with synthesizable test bench.

- user_design:
This folder includes the design without test bench modules.

But actually i don't see any important difference between these folders except the name of some files! The top module of both folders have instantiated the controller and the traffic generator for testing. So which module is appropriate for start of my design?! Both are too complicated that i can't use in my design!
Any hint please?

Thanks in advance

Yes, the designs that the MIG generates are way too complex to be a good reference implementation!

If you're using the Spartan-6 MIG, here's a guide on using the MIG with a simple example:
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Hi Joelby,

How different is the designing for Spartan 6 and Virtex 6 is.
Since I have to design in the Virtex 6 FPGA the MIG


I haven't used the Virtex-6 MIG so I can't tell you for sure. The MIG is different for every FPGA family, but I think that if you are already familiar with Xilinx cores in general and HDL you shouldn't have much trouble moving from one MIG to another, at least if you are building a design from scratch and don't have to support multiple MIGs.

Example design gives you test bench also where u can simulate and see the result...

By using MIG u can generate core for specific device.No need to convert one device code to another one..

Thank you both for reply.

ok I understand that.

One more question. I don't know about Spartan, but in Virtex MIG design, it ask for the addressing scheme to be
either ROW/Bank/Col or Bank/Row/Col.

Which one is better and also the addressing that we will do, we should treat it as a normal addressing. right?
What is the purpose of these two ?

Looking for response in this matter.

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