MIG as DDR2 controller, virtex5

[hastidot]

Hi all
I'm using DDR2 controller, MIG for virtex5 FPGA.
I have encountered an error which I don't know how to solve.
I will be appreciative for any help:
ERROR:NgdBuild:924 - input pad net 'SysClk' is driving non-buffer primitives::sad:

 

[mrflibble]

For once the error message describes the actual error. You need an IBUFG there.

quick fix:

module whatever (
(* BUFFER_TYPE = "IBUFG" *) input SysClk, // in your module port declaration
//etc

You may also want to check the XST manual or google for BUFFER_TYPE.

 

[hastidot]

Thank you for your reply
But I didn't get the pint. How can I use IBUFG for SysClk. Should I connect the Buffer's output to DCM input?

 

[mrflibble]

This SysClk thing is an input pin right? Or let me put this another way, it would help if you could give more info on SysClk. Where do you use it, modules, etc. Does SysClk happen to be a signal that you want to connect to the input of a clocking resource like DCM or PLL? If yes, then you need an appropriate buffer.

 

[hastidot]

Yes. SysClk is an input port. I want to use it as the input clock for DCM block. so I used it as:
clkdcm iclkdcm (
.CLKIN_IN(SysClk),

But that error appears. How can I use Buffer in order to dispel the problem?
Thank you in advance for your help

---------- Post added at 15:08 ---------- Previous post was at 15:08 ----------

Yes. SysClk is an input port. I want to use it as the input clock for DCM block. so I used it as:
clkdcm iclkdcm (
.CLKIN_IN(SysClk),

But that error appears. How can I use Buffer in order to dispel the problem?
Thank you in advance for your help

 

[mrflibble]

Well, check out the documentation for the DCM/PLL inputs. It will mention what kind of inputs it does and does not like. It does not like regular boring inputs. It likes global clock nets. Which is why you need the ibufg. And you probably have the "Insert IO Buffer Thingies" option turned to OFF, or otherwise the tool would have inserted the IBUFG for you. Either way, try that line I gave you, that should solve the problem.


And no, not in that line with the module you post there. Where does sysclk come from? Is it an input from an external cmos oscillator? You want the IBUFG on the top level module, if this SysClk is coming from outside the fpga.

 

[hastidot]

Thank you so much. It was really helpful
Yes it is coming from an external oscillator.I will check it
Thanks again

 

[hastidot]

Hi there
I just tried to use IBUFG ( or either BUFG) for the Sysclck which is connected to CLKIN pin of the DCM. But the following error appears :
NgdBuild:770 - IBUFG 'CLKIN_IBUFG_INST' and BUFG 'clkbufg' on net
'SysClk_BUFG' are lined up in series. Buffers of the same direction cannot be
placed in series.
It seems that in DCM HDLsource code CLK-IN is driven into a buffer.
I don't know how to solve the problem according to following error:
NgdBuild:924 - input pad net 'SysClk' is driving non-buffer primitives::-(

 

[kirill]

hi
You have an input pad that is connected to something other than an input buffer. Check it.

 

[permute]

What is the input pad? eg, IOX_P_GCLK? or something similar. you want to have the _P and _GCLK attributes on the clock inputs.

 

[voho]

Look if SysClk is connected in your virtex5 in pin I/O GlobalCLK