Yes, rightIf I understand you correctly, you would use a component/transistor/other element later on but you want to place its place in schematic now.. right ??
In order to do this, you don't have to place any element for them, place simply a Pin and transfer your schematic to layout..
But for auto-generating the layout, the MGAP is indeed a possible placeholder for the SMD. It can be set to create a defined gap, so that auto-generated layout continues with the next elements "after" that SMD.In order to do this, you don't have to place any element for them, place simply a Pin and transfer your schematic to layout..
How to import the elements like transistor in the layout window? And also each element has specific dimensions to be fit perfectly during the fabrication process. How to control that? Are there any direct way to replace transistor and lumped components with other components in schematic window in ADS so that after transferring to the layout I can see clearly the places of those components. ThanksThere is nothing to be explained more... Simply place a PIN in schematic view and move on..You can place you layout element in layout view between those PINs later on..
Or simply leave unconnected.. it will work too..
For the transistor, I am using CGH40010F provided by cree. They offer ADS model which can be used in the schematic window but it does not have a layout view in the layout window. So, Could you place explain clearly how to draw or model it in the layout window if it is possible? Also, how about lumped components, In the schematic window I am using the normal one, but how with it in the layout window? Is only gaps enough for that? ThanksFor many components, you also find complete libraries (designkits) with components predefined, which have electrical model and layout.
If you want to create that yourself, create a cell for each componet type with
- schematic view that has the electrical model and pins
- layout view where you draw the footprint/pads from polygons, with pins placed at the external connection
- symbol view copied from a standard symbol or created yourself in the symbol editor
The number of pins in layout and schematic and symbol must be the same.
Then, you can place this cell (representing the component) into the main schematic.
Will you send your design to Cree to make manufacture ?? If it's so, you have to use PDK of Cree otherwise it doesn't make sense to place a layout view of active device.In the schematic window I am using the normal one, but how with it in the layout window?
It seems he relies on auto-generated layout (from schematic) and doesn't know how to place components or artwork in layout manually. So in that case, having the component footprint will help in layout.otherwise it doesn't make sense to place a layout view of active device.
The problem is when we do the fabrication. How transistor will be fit perfectly if its dimensions not defined?Will you send your design to Cree to make manufacture ?? If it's so, you have to use PDK of Cree otherwise it doesn't make sense to place a layout view of active device.
Place PINs for DGSS connections and do your EM simulation if it's your real target..
I said that use PDK of Cree, not model standalone..The problem is when we do the fabrication. How transistor will be fit perfectly if its dimensions not defined?
You're discussing the wrong workflow. He uses a complete device, and doesn't design his own chip.I said that use PDK of Cree, not model standalone..
Look up the footprint size in datasheet and arrange input & output lines in ADS layout accordingly. Or use the method discussed above to create a footprint in ADS.The problem is when we do the fabrication. How transistor will be fit perfectly if its dimensions not defined?
Thanks for detailed explanation. For CGH40010F device, as the source pin is at the back side of the device as shown in the datasheet. Then, how to be grounded especially during momentum simulation. Usually when the pin is in front, we do path to ground and connect the pin to that path, But in this case source pin is not in front. ThanksADS has always had capabilities to allow the user to define layout footprints for devices when none is otherwise available. This capability was inherited from predecessor platforms going back 30+ years. It shocks me that users do not know this.
Firstly, let me state that the request here is to cover a CGH40010F FET device and other lumped components so this implies discrete surface mount components and not integrated devices. Therefore discussions about PDKs is less relevant.
For passive surface mount components, like resistor, capacitors etc., The simplest strategy is, as was originally requested, just leaving a gap is a reasonable starting solution. So the problem here is that simple ideal resistors (R), inductors (L) and capacitors (C) do not have associated artwork so simple auto-updates of the layout will not be useful. ADS accommodates this situation by providing a library of components for "Lumped-With Artwork". There is a palette with these components and they are also listed in the Component Library browser. The simplest solution here would be to use components like R_Space where the user can define the ideal resistance to be used in simulation and the L1 parameter sets the size of the gap. There are similar components for inductors and capacitors. These are ideal simulation models so if anything more complex is required for that then more elaborate method will be required.
Once you browse this library it will be possible to see that this gap method is just one of the simplest. There is also a set of the same elements with Pad1 artwork. These elements will draw a pad for the artwork where the user can define the dimensions of these pads. The simulation model is still a simple ideal component and the pad itself is not included in the simulation. You would need to include some sort of EM simulation for that case.
There is also a additional resistor component, R_dxdy, where the user can not only set the gap dimension but also an offset (sideways) spacing.
View attachment 156040
For the CGH40010F device, the method is more complex as there is not similar layout library as with the passive devices but still it is relatively simple. A simple gap method can still be utilized. This will utilize the same 2 pin method, I shall ignore the Source Pin(s) in the layout as this is a flange mounted device so the implication is that this connection must be mechanically grounded.
According to the CREE datasheet the gap should be around 0.160 inch/4.065 mm. In the workspace that you are using the device create a new layout design with a suitable name, e.g. gap4065um. In this new design place 2 pins, pin #1 (arrow pointing to the right) at 0 um, 0 um and pin #2 (arrow pointing to the left) at 4065 um, 0 um or at a location of the required gap relative to the origin at 0, 0 if something different was preferred. Save this design.
In the schematic design for the amplifier right-click on the transistor symbol and select the command Component > Edit Component Artwork... from the pop-up menu. In the Component Artwork dialog select the Artwork Type of Fixed and then select the browse button. From the current workspace library select the "gap4065um" cell that you created in the previous step and select the layout view of that cell for the Artwork Name. Save the updated schematic.
Now you should be able to generate the layout for the complete design that includes the necessary gaps for the lumped devices.
Once you are familiar with this method then it should be possible to draw additional structures in the artwork design for the FET, that is currently just the simple gap, to include actual outlines of the flange device and have that representation appear in the full layout view.