asic_verification_learner
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Hi ,
Would anyone suggest me , i need to develop micro-architecture of my design , i came to know that efficiency of RTL code depends upon micro-architecuture , so what are the techniques/rules/guidelines , ASIC designers follow while developing micro-architecture for their assigned specification.
how i need to divide the whole logic into partitions .... ?
techniques/guidelines , i came to know are
minimum data,, should flow ,, from one clock domain to another clock domain
we need to extract the common functionality ....
....
..
please help me , in this issue
Thanks in advance.
Would anyone suggest me , i need to develop micro-architecture of my design , i came to know that efficiency of RTL code depends upon micro-architecuture , so what are the techniques/rules/guidelines , ASIC designers follow while developing micro-architecture for their assigned specification.
how i need to divide the whole logic into partitions .... ?
techniques/guidelines , i came to know are
minimum data,, should flow ,, from one clock domain to another clock domain
we need to extract the common functionality ....
....
..
please help me , in this issue
Thanks in advance.