akbarza
Full Member level 2
hi
i saw a pic that show transistors in an opamp as rectangle or square blocks that they are layout side by side( unfortunately i missed the pic.). the blocks have different sizes.
i know that the blocks connections and placement must have smallest total area and lowest time delay.
my question is on which method they are layout ? is there any mathematical method to place some rectangle to have smallest total area?
in a large view: if we have some elemnt as opamps, capacitors and..., how place them to have smallest area ?
if we have some other constrain as smallest delay or em competibility, how place them with this constrains? is there any method?
thanks
i saw a pic that show transistors in an opamp as rectangle or square blocks that they are layout side by side( unfortunately i missed the pic.). the blocks have different sizes.
i know that the blocks connections and placement must have smallest total area and lowest time delay.
my question is on which method they are layout ? is there any mathematical method to place some rectangle to have smallest total area?
in a large view: if we have some elemnt as opamps, capacitors and..., how place them to have smallest area ?
if we have some other constrain as smallest delay or em competibility, how place them with this constrains? is there any method?
thanks