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Methods for fixing EM violation????????

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vlsi_deepa

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Hi,
I am doin backend flow for SOC design(130nm tecnology) using Magma tool.
Currently working in EM Analysis.... Can Anybody tel me in detail, how to fix, wire
EM Analysis ?
We should create meshes & Rails carefully which shouldnt create any problem related to EM.If it is,how to calculate meshes and rails width?

Can anybody help me?

Deepa.........
 

phutanesv

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Deepa,

Hope blast fusion and blast noise fixws this problem automatically.

by using VCD files.

not sure just a sugesstion
 

pinkesh2001

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Deepa,

When doing EM analysis in Magma, the report clearly shows the hotspots where the EM violations are. if you go through the report properly it even says that what is the actual current density and required density. It also gives suggestion on adding vias or increasing the width of metal.

You can take of EM violation upfront while designing the power-grids. Synopsys paper regarding the power calculation is very good paper.

Hope this is clear.

Regards,
Pinkesh
 

    vlsi_deepa

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roy_ece

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hi,
Deepa .As far as EM problem is concerned it is the same in any tool.The Best possible solution can be to increase the number of VIAS (VIA array) if possible .The detailed info about this can be seen in any Rules document of Fab suppoting your design.Power routing also needs to be checked once again,like increasing the width of stripes . And Floor planning techniques like placing the module which consume more power near the power stripes.If possible place apower ring around such a module.Hope All these techniques help you fix the problem.
Regards,
Roy

Added after 3 hours 41 minutes:

hi,
While doing the EM , the check should be done with Average value of current but not with the peak value. The reason, the more average current the more heating hence exacerbates EM violation.The average value is +ve or -ve depending on the direction of your current. If you have some DC current in the design then the total EM should be checked against DC+Average value. As you have taken the peak value normally you will see the EM violations as it doesn't give the actual value of current flowing. Conform the same from your Manager.
Thankyou,
Regards,
roy

Added after 46 seconds:

for more information read the paper

http://www.cadence.com/whitepapers/emir_wp.pdf

Added after 13 minutes:

hi,
see this attachement for calculating strip width.
https://www.edaboard.com/viewtopic.php?p=634707#634707
 

vlsi_deepa

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Hi Friends,

Thanks a lot for ur reply....... It was very useful to me............

Thanks,
Deepa..........
 

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