Method for monitoring process variation of PMOS and NMOS

[bageduke]

I want to implement process monitor on chip. The easiest way is to count ring oscillator frequency to get process information. But in this case, I cannot tell it's PMOS or NMOS variation.

Is there any simple way to monitor process variation of PMOS and NMOS separately?

thanks

 

[palmeiras]

Re: CMOS process monitor

Hi bageduke,

You have the option to implement NMOS-only, and PMOS-only ring oscillators. In this case, you increase the power consumption because the active load always conducting.
In addition, you can use stacked-pair transistors. Two transistors connected in series, with the gate and bulk connected. Monitoring the output voltage (drain of M1 and source of M2) you have information about variability. Take a look in the following references:

[1] Rahul Rao; Jenkins, K.A.; Jae-Joon Kim, "A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement," Solid-State Circuits
Conference, 2008. ISSCC 2008. Digest of TechnicalPapers. IEEE International , vol., no., pp.412-623, 3-7. 2008.

[2] Wils, N.; Tuinhout, H.P.; Meijer, M., "Characterization of STI Edge Effects on CMOS Variability," Semiconductor Manufacturing, IEEE
Transactions on , vol.22, no.1, pp.59-65, Feb. 2009.

[3] Test Circuit for Evaluating Characteristics Mismatch in Metal–Oxide–Semiconductor Field-Effect Transistor Pairs by Estimating Conductance Variation through Voltage Measurement Mamoru Terauchi and Kazuo Terada Jpn. J. Appl. Phys. 47 (2008).

Finally, you can have a matrix of transistors.... and measure each of them in order to have the statistic distribution.

Regards,

 

[leo_o2]

Re: CMOS process monitor

In fact, both pmos and nmos include many aspects for characteristic, such as Vt, mobility, capacitances, on-resistance and so on. For different aspects, different methods are needed for monitoring. In most cases, foundries will have test keys in scribe line for process monitoring.

 

[Prithvee]

Can anyone explain me how the RO modules on a chip monitors a chip's performance? Especially, predict the speed of operation of the chip.


Thanks

 

[leo_o2]

Basically RO is composed of inverters. It reflects PMOS and NMOS switching characteristics. So it mimics the process and temperature variation for the other logic circuits.