Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
when all the I/P constraints for a flop such as setup & hold time are meet, then FF produces faithful O/P. However when any one of these constraints is not meet then O/P gets into metastable state which we also call as unstable state (undefined state) from there it may achieve logic O/P as 1/0 & we normally say that O/P state can not be predicted but high end designs can predict the O/P state after it once achieves metastable state I've some stuff about this I'll attach that shortly
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.