LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity hello_world is
port (
clk : in std_logic;
-- reset : in std_logic;
led : out std_logic
);
end entity hello_world;
--
architecture rtl of hello_world is
constant CLK_FREQ : integer := 20000000;--20000000
constant BLINK_FREQ : integer := 1;
constant CNT_MAX : integer := CLK_FREQ/BLINK_FREQ/2-1;
signal cnt : unsigned(24 downto 0);
signal blink : std_logic;
begin
process(clk)
begin
-- if reset <='1' then
-- blink <='0';
if rising_edge(clk) then
if cnt=CNT_MAX then
cnt <= (others => '0');
blink <= not blink;
else
cnt <= cnt + 1;
end if;
end if;
end process;
led <= blink;
end architecture rtl;
I tried to run this programm to blink led in both quartus and fpgadvantage from mentor, but it was only successfull in quartus..anyone has idea about this??