Memory Map Decoder for 8051 variant

[czpir]

Hi All

I want to design a memory map decoder for the following scenario.

I am using a 8051 variant with a special memory interface. This has 22 address lines and 8 data lines. This means that potentially 4 mb of memory or i/o can be interfaced.

I want to add 2 mb of SRAM and also 32 bytes of i/o to this microcontroller. This is what I have done

I have connected the address lines A0-A4 to the i/o device and data lines are D0 to D7, I have connected the address lines A0-A21 to the same ones on the SRAM.

This leaves the address line A22 free, I also have an active low CS line which would go low for any i/o or memory access. I also have WR and RD lines.

Any help for on deriving the the CS line for the SRAM and I/O device would be appreciated, can this be done using the 74138 or other ?

CZPIR.

 

[usbman]

For a CS on 2 MB boundary simply connect A20 to CS of your Ram
This will give you 2 MB starting at 0x000000 (connect RD+ WR+ A0..A20 to the SRAM )
Your IO could be made with the inverted A20 then the IO will start at 0x200000.

usbman

 

[czpir]

Connections for the I/O

UsbMan

Thanks for the reply. I would appreciate more on the following:

Can the I/O be connected using A0..A4 ? I would use the inverted signal of A20 for the CS for the I/O. Can you advice me on the inverter chip for a 3volt design ?

I guess that the I/O would begin at 0X2000000 and not at 0X200000 as you have mentioned.

I do notice that the CS line on my microontroller would not be used. This is a negatively active line that would go low when I/O or RAM access is made.

Regards

CZPir