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memory in rtl verilog code

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Member level 3
May 7, 2002
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how to i do ?

I write a rtl verilog code, there is a memory in code,if i use design analyzer to compile ,,because i am told that memeory can not be compiled by tools. so how will i do ?


Usually, memory is cann't be compiled from RTL verilog code. It is provided by memory vendor. artison have a memory tools to generate fifo,sdrm and etc. The tools can generate rtl verilog vhdl code for simulation. synopsys db format file to use directly, pdf manual, ........

if i don't compile memory ,so how do i deal with it in design analyzer ?
i isolate it when to compile?and how to cope whith read/write logic and timing simulation ?
i can not understand it ?

U may ask ur design service company or memory compiler to generate one .db or .lib for this memory macro cell. Its work is same as ur standard cell's .db .
This .db or .lib include the design rule, timing information , pin driver/load. So u can link this library with ur RTL code.

My prefered methogology is to use a wrapper for the memory. This
wrapper provides the generic interface (I/O) as required by your design.
Then you create at least two memory lib.
1) Behavioral: This the is RTL implementation of the memory. You use it
during development because it is much faster.
2) Vendor models: This the memory model that you receive from the
ASIC vendor. You use the same wrapper and simply force inactive the
signals that you do not need on vendor model inside the wrapper.

As you can see the top module of the two models have the same inteface.
So by putting the behavioral and the vendor models in saparate libbraries
one simply select the library before simulation to go faster or to do a
timing simulation. It is also very usefull if you have many vendors to try.

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