Memory Control Block DDR3 with Spartan-6 (VHDL/ Tutorial)

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samthany

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Hi friends,

Could somebody provide me sample designs or projects of Spartan-6 DDR3 Memory controller interface with MIG (Memory Interface Generator) ?

The reference design from Xilinx is confusing and complicated..Please Help me!

Thank you!
Sam
 

about creating ddr3 ram block(shematic)?
in other word about how you can use mig?
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sorry for my bad english
 

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