Memory Compiler restrictions

[ivlsi]

Hi All,

What restrictions for Memory Compiler do exist? Why is not possible to generate memories of any size?

Should a vendor provide a catalog of the available memories?

Thank you!

 

[rca]

The memory compiler documentation indicate the possible range.
And usually when you start the compiler memory in GUI mode, the range is also displayed.
limitation occur on:
number of word width
number of address
mux
mask write enable (on 32bits you could writte byte by byte or bit by bit dependant of the compiler)

 

[ivlsi]

Thanks. As for the Memory Compiler, does it generate the memories, which already exist in the vendor libraries? There are STD cells library, should also be the Memory libraries?
Why the Memories are restricted to a minimum size? What about the single row memories?
As for the STD cells, there are masks for each of them. Do the ASIC vendor have masks for all the memory combinations or it should produce them each time according to the Memory Compiler results.
Thank you again

 

[rca]

depending of ram type, eeprom typer, flash type, OTP, the layer needed could be as for the std cell or need specific one, that are really dependant.

you could see on tsmc website what are available for each technologies.

one single row memory could be implemented with flop for less area than a ram instance.

do you know on which techno?

 

[ivlsi]

Yes, as for the tech process, it's 40LP (40nm low, power).

BTW, when it's worth to choose flops and when memory? let's say for 256*4 array, is it better to implement it as flops or memory?

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you could see on tsmc website what are available for each technologies" - searched the site, but did not find an answer. Could you provide a relative link please? Thank you

 

[rca]

256*4, you know the area of scan-flop without reset and without data gated, and you could generate a memory of 256*4, and compare.

you could find also from IP vendor like: https://www.synopsys.com/dw/emllselector.php.

 

[ivlsi]

Thank you!