I want design a memory circuit for AVR microcontroller , its cosists of a latch and a 8k ram , 2 decoders , 7 segment , and a counter
anyone help me find a full graph of the design
THANKS
goto ethernut project, fetch its schematics and get some idea how the mcu is attached to ram (though neest revision includes cpld as address decoding circuitity ). Same information must be in schemtics for stk500 501 .