Memory bandwidth considerations in DDR interface design

[seeya]

System designers typically measure memory performance requirements in a combination of two situations: a statistical analysis of bandwidth averaged over a large sample of expected cycles, and a deterministic analysis of a smaller set of specific cycles for "must complete" tasks. Some applications will be wholly in one or the other of these realms, but most will be some combination of the two.

The performance requirements are bounded by several constraints and choices: memory size required for the system, I/O bus width, total pin count devoted for memory subsystem, power budget, need for parity or error correction, cost. The synchronous memories widely in use today make calculating bandwidth both statistically and deterministically a mostly straightforward task if one is familiar with read and write turnaround times for both SRAMs and DRAMs, and the effects of bank activation in DRAMs.

Please ref:h**p://www.eedesign.com/story/OEG20030609S0067

 

[mami_hacky]

Hum! have you ever designed a memory controller your self? Do you have any experience with DRAM devices, or have you ever tryed to obtain a specific bandwidth from memory components? Do you know the difficulties of memory controller design in VLSI? If some body tell you to design a 25 Gbits/s data storage unit using available DRAM memories, what will you tell him? is the work completely impossible? or there are some tricky solutions?