[Memories] Bus TurnAround Cycle

[ivlsi]

Hi all,

How to eliminate the turnaround cycles in Memories.

WiKi: turnaround cycles are number of clock cycles it takes to change access to SRAM from write to read and vice versa.

Thank you

 

[sharath666]

I am not sure about SRAM. But memories usually have fixed relationships between sequences of commands. The maximum throughput possible will depend on how the controller is implemented.So if you want to minimize turn around cycles, come up with a good controller...