Measurement of power supply inductance

[FreshmanNewbie]

In this tool, or any PDN tool for that matter, I understand that the value of plane capacitance can be calculated with the layout stack-up information (Di-electric thickness, overlap area of planes and di-electric overlap area).

But, any idea on how to calculate the "power supply inductance" value?

 

[D.A.(Tony)Stewart]

3D Geometry is fairly scalable to reactance for both C and L.

For L the conductor geometry per cm length is complex but roughly as follows from my calc's.

 

[KlausST]

Hi,

you talk about the capacitance of copper planes on a PCB... It´s easy to define the copper area.

But what is the meaning/definition of "power supply inductance"?
For an inductance you need a loop for current flow, where the forward current generates a magnetic field and the return current also generates a magnetic field .. and both fields may compensate each other - or not - or add up - depending on the mechanical construction.


Klaus

 

[dick_freebird]

The control loop of linear or switching power
supplies acts similarly to, but far outweighs
the physical magnetics present. It must dominate
the tank, that is its duty. In a switcher the current
mode control scheme wants to force inductor
current to constant (given zero error voltage)
above and beyond the inductor's natural action
to do the same.

I'd "load-slam" it and observe time constant
and settling behaviors. The character of these
is what you're more after as a designer or user
of a power supply. If you characterized
additionally for C and R "effective" values
then you'd have something.

 

[D.A.(Tony)Stewart]

What should Ls be? That depends on voltage/current, load/source impedance ratio thus also Resistance / Inductance ratio. (R/L=1/T = 2f (triangle)

For a high breakpoint f in a DC low pass but impedance rising with f, I think in terms of high breakpoint f, consider R/L = 10k approx.

However Q's will be high with no load and no source resistance so we need damping resistance, Rs but low loss, thus the tradeoff in PDN filter design.

We know step load regulation error is Rs/(Rs+load) for low % = source/load impedance, used to determine source impedance from step load error or visa versa.
The max. step load specs affect your total voltage error budget mught be 1% max or less so Rs can be specified from your current load specs.

This is one way to determine Rs & Ls.

But to match impedance from source to load we need a conjugate match so choice of caps is critical.

In the old logic design days (CD4xxx) when step currents were lower, C was lower, RdsOn was higher so typical solutions were simple depending on source of ripple, we could just choose 10 uF , 0.1 uF and 1 nF or something like this all in parallel and not worry about ESL. But now with much lower switched load ESR caps and uC with lower RdsOn and higher C ripple, higher BW , shorter logic rise times near 1~2 ns more or less.

Now PDN results can cause serious resonance gains with light loads (low damping) that source impedance and ground + power plane impedane is critical.

 

[FreshmanNewbie]

The control loop of linear or switching power
supplies acts similarly to, but far outweighs
the physical magnetics present. It must dominate
the tank, that is its duty. In a switcher the current
mode control scheme wants to force inductor
current to constant (given zero error voltage)
above and beyond the inductor's natural action
to do the same.

I'd "load-slam" it and observe time constant
and settling behaviors. The character of these
is what you're more after as a designer or user
of a power supply. If you characterized
additionally for C and R "effective" values
then you'd have something.

Can you tell me how the control loop of the switching power supply dominates the tank circuit (output inductor and output capacitor)? And more importantly, why should the output tank circuit (L and C) dominate the control loop of the switching power supply?

 

[dick_freebird]

If you look at an unloaded buck output from t=0,
you'll see the LC tank fundamental sine wave
develop from a plain PWM stimulus. What you
want is to get to setpoint Vout, and then flat-top.

So the control loop must respond with more
authority (because inductor by setpoint is
"spun up" with more current than it needs to
get there) in less time than it takes to overshoot
beyond spec tolerance.