savithru
Member level 1
hi
I am using the verilogA model for the frequency divider given in the pdf "Hidden State in SpectreRF" by Ken Kundert,
Designer’s Guide Consulting, Inc.
Author has used the following
module divideByN(pout, nout, pin, nin);
Here he define the module by the name divideByN with pout, nout, pin, nin as ports.
But I could not understand what are these Pout and Pin ports.
kindly reply.
Regards
SavithRu
FUI, this model is available in the rfLib.
I am using the verilogA model for the frequency divider given in the pdf "Hidden State in SpectreRF" by Ken Kundert,
Designer’s Guide Consulting, Inc.
Author has used the following
module divideByN(pout, nout, pin, nin);
Here he define the module by the name divideByN with pout, nout, pin, nin as ports.
But I could not understand what are these Pout and Pin ports.
kindly reply.
Regards
SavithRu
FUI, this model is available in the rfLib.