Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

meaning of ports in VerilogA model for Freqency divider.

Status
Not open for further replies.

savithru

Member level 1
Joined
Aug 18, 2005
Messages
36
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,628
hi

I am using the verilogA model for the frequency divider given in the pdf "Hidden State in SpectreRF" by Ken Kundert,
Designer’s Guide Consulting, Inc.

Author has used the following

module divideByN(pout, nout, pin, nin);

Here he define the module by the name divideByN with pout, nout, pin, nin as ports.

But I could not understand what are these Pout and Pin ports.


kindly reply.

Regards
SavithRu

FUI, this model is available in the rfLib.
 

You can open the model and check the comments. Most probably the description will be written there
 

Thank for replying..

I got it now....How ever there is non descrption in those comments.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top