MDAC Circuit Issues for an 8 Bit Pipelined ADC

[ashourism]

Hi

I am working on a Pipelined ADC

1. I have built an ideal system that gets an ENOB of 7.99
2. I created a Folded Cascode amplifier that settles in 3ns with GBW 200MHz and Gain 61dB and put it into the system then i got an ENOB of 7.8

but now i am trying to replace the DAC and the switches with real components however i am facing very strange issues and problems and i hope to know if someone can help me with it

I will try to be organized as much as possible and as informative as possible in this post so i apologize for its long size

General Notes

1. Supply Voltage = 2.5V
2. Common Mode level 1.2V
3. Vref = 1.5V
4. -Vref = 0.9V
5. Fsampling = 12.5MHz
6. Input signal is a differential sine wave of 600mV peak to peak and frequency 765KHz
7. All testing done here with an Ideal amplifier of GBW = 200MHz and very high gain

1. The Ideal MDAC Stage

#All blocks here are built using VerilogA and switches are Cadence built in Relays

##The Ideal Stage Schematic :
##The Ideal Stage Transient Response :
##The Ideal Stage Tran. Response Colour Code :

2. The DAC Circuit

##Unloaded DAC Circuit Schematic and Its transient Response
->The DAC Circuit Schematic (with color code) :
->The Unloaded Transient Response :

3. The DAC in MDAC Circuit with Switches

## The Non Ideal System Schematic :
## The Non Ideal System Transient Response :
## Response Color Code :

4. The DAC in MDAC Circuit with Switches with an attempt to correct DAC Output with a 2pF Cap

## Schematic:
## Output :

5. Effect of Correction on Whole Stage

## The Non Ideal System Transient Response (Corrected) :
## Response Color Code :

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ENOB with switches and Non_Ideal DAC drops to 0.5! and signal output is distorted significantly, I really don't know where is the problem, i have tried all of the following

1. custom size for NMOS inside DAC and outside this has worked to get a neat DAC Stage and avoid clock feedthrough and charge injection
2. Using Transmission Gates
3. Using Transmission Gates with 1/2 W dummy transistor on both sides of the N and P Mosfets
4. I don't understand the cause of the glitches and i hope someone can help me with it?

Thanks

 

[Dominik Przyborowski]

1. OPamp issue. If You calculate mdac response with finite opamp gain You will get an minimum open loop gain for opamp and adc resolution. For 8 bit it should be around 80dB but I'm not sure.

2. I don't know a dc voltages at nets connected to your switches, but my first thought is that Vgs on your switches is not high enough to provide correct operation. In addition some of them has minimum width 160nm and higher length (340nm) so it doesn't look good.
Try to use tgates instead of single nmos with minimum length fets (if low threshold devices are available in your technology use them) and with reasonable width providing small enough resistance and not to high capacitance.

3. To avoid glitches try to use non-overlapping clocks.

Check also behaviour of ideal system with non-ideal switches.