Maximum temperature allowable for FET?

[noisepic]

When I measuring temperature on the surface of the FET, it up to 95 deg? I wonder how much is allow able, inside for temp junction up to 175 deg. But 95 deg seem to high for its lifetime. So maximum allowable temp I must design?

 

[CataM]

I wonder how much is allow able

Estimate the junction temp with the thermal resistances/impedance , if it is the case.

So maximum allowable temp I must design?

For a maximum Tj=175ºC , in theory if you have Tj=174.(9), you are good.
Capacitors usually have a lifetime equation in some datasheets... I am not aware of such of these in semiconductor devices.

 

[KlausST]

Hi,

The FET datasheet should contain temperature specifications. Read it.

Klaus

 

[dick_freebird]

This all depends on expectations, construction and
what limits reliability under those conditions. I have
personally run integrated JFETs and MOSFETs at
300C for very long periods of time and everything
worked just peachy (no doubt in part because the
process technologies were developed for HiRel
applications). But power devices are another thing
entirely, with internal temp rise on top of case
temp and the potential for some designed-to-the-bone
feature such as body access resistance being just
barely OK at 175C, and avalanche burnout at just
a hair more temp*voltage, perhaps, when Rbx goes
higher along with parasitic BJT leakage and gain,
while the Vbe (Vbs) needed to initiate snapback
goes down.

Specs tell a story. They leave out the pictures
sometimes.

 

[noisepic]

Hi,

The FET datasheet should contain temperature specifications. Read it.

Klaus

It's not simple as your answer!

 

[c_mitra]

The datasheet tells you about the thermal resistance of the device. That is important because you do not have physical access to the semiconductor junction.

I guess you are having problem with the thermal resistance. Let me try to explain in simpler language.

Resistance is measured by force per unit inertia. In this case, the force is the temp difference and the flow is heat transferred per unit time (measured in watts).

We consider the max temp at the junction as the value specified in the datasheet. Say this value is 125C. Let us say the room temp is 25C. The temp gradient is therefore 100.

Let us also assume that the thermal resistance (depends on the package type) is 10 (deg/W). That means that the flux is 10W and your device is happy to dissipate 10W power under this condition.

If the room temp is 50C, then the device can dissipate only 7.5W.

If you add a heat sink to the device, the thermal resistance will fall. It will be able to dissipate more power.

 

[noisepic]

I understand this, as someone answer before we able to design to meet junction temp is 174.9 deg, and the bigger heatsink make the fet top case less thermal (low temperature). So the right anwer I think is here, base on Junction- packaga thermal dispassion we will estimate the top case temp.

 

[c_mitra]

I understand this, as someone answer before we able to design to meet junction temp is 174.9 deg...

Sorry, I did not understand the question clearly enough....

 

[KlausST]

Hi,

It's not simple as your answer!

Maybe you don't find it easy to calculate, but it should be easy to read.

Why don't you simply give a link to the datasheet, or upload the datasheet, then we can tell which values to use and how to calculate with them.

Klaus