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> It is said that u need to consider maximum setup time and minimum hold time.
can any one explain this ????????
while doing analysis on setup time , the comparision is done at the next pulse , hence we use max. delay analysis.
However in hold analysis there comparision is done at the same clock edge ,so min. analysis is used.
Between two register sometimes there is combinational logic, this logic has to be necessary overcame before of the sensible clock front. The setup time is the time before the datas in output of the combinational logic has to be ready before the sensible clock front. This time exist for tecnologic reasons; when you use a hardware synthesizer in your design technological libraries are required, so in these there are specified both setup and hold time. The reason for the hold time is the same, and the hold time is the time that data has to be stable later than a clock front, before that the hardaware can process this data