Maximum possible width for type "unsigned"

[shaiko]

Is there a width limit for the width of an "unsigned" vector type in VHDL ?

 

[K-J]

Is there a width limit for the width of an "unsigned" vector type in VHDL ?

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
Therefore the allowable width of an unsigned is the range of naturals which is 0 to 2147483647.

Kevin Jennings

 

[shaiko]

BTW ,
If you set it to single bit length ,
Will it have all the properties of an "std logic"?

 

[xtcx]

Is there a width limit for the width of an "unsigned" vector type in VHDL ?

I think, you can go upto a maximum of 2³²
That is the range.....

 

[K-J]

BTW ,
If you set it to single bit length ,
Will it have all the properties of an "std logic"?

If by 'properties' you mean can they be used in the same manner then the answer is 'no'. One bit of a type that is defined to be an array of some other type will be used in the code in a different way than the base type itself. Some examples:

---

Code VHDL - [expand]
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signal xyz_vec: std_logic_vector(0 downto 0);
   signal xyz_bit: std_logic;
begin
   xyz_vec <= xyz_bit; -- This is an error becuase the left hand side is a different type than the right
   xyz_vec(0) <= xyz_bit; -- OK 
   xyz_vec <= (others => xyz_bit); -- OK 
   xyz_vec(0 downto 0) <= '1'; -- This is an error becuase the left hand side is a different type than the right 
   xyz_vec(0 downto 0) <= "1"; -- OK 
 
   if (xyz_vec = '1') then -- This is an error also, comparing different types 
   if (xyz_vec = "1") then -- OK

---

Not sure if that's what you're asking about for 'properties'.

Kevin Jennings

---------- Post added at 13:59 ---------- Previous post was at 13:55 ----------

I think, you can go upto a maximum of 2³²
That is the range.....

Not quite. 2147483647 = 2^31-1

 

[xtcx]

yeah sorry about 32

 

[FvM]

Although I appreciate an exact answer, I wonder if numbers above available logic cell count are of practical interest.

 

[shaiko]

I wonder if numbers above available logic cell count are of practical interest

No...just for general knowledge.

The limit for integers ( 2^31 - 1 ), is however of a practical interest.
I don't see any good reasons for inffering such a limit - especially with 64 bit systems becoming more common.

 

[K-J]

No...just for general knowledge.

The limit for integers ( 2^31 - 1 ), is however of a practical interest.
I don't see any good reasons for inffering such a limit - especially with 64 bit systems becoming more common.

The limit was established back when VHDL was first defined and standardized in 1987. Why the language hasn't evolved to include larger integers I don't know (but it has been asked many times in several forums). But a more practical question might be, what are you planning on doing that can't be done with signed/unsigned which have the much larger numerical limit of 2^( 2^31 - 1 )? The initial drawbacks I see are:
- You can't have a single loop variable count that goes that large (i.e. for i = 0 to 2^33 ...)
- You can't compare to a literal integer that large (i.e. if my_unsigned = 2^33 then...)

Simply working with large signed/unsigned with math operations, logical operations, etc. is not a problem.

Kevin Jennigns

 

[shaiko]

But a more practical question might be, what are you planning on doing that can't be done with signed/unsigned

Nothing really.
I have a rule - to use only integers for counters.
Somtimes 2^32 - just isn't enough.

 

[std_match]

I have a rule - to use only integers for counters.
Somtimes 2^32 - just isn't enough.

Why integers for counters?

Advantages with using unsigned as counters:

1. No size limit

2. Wraps automatically

3. Better size checking. If you test an integer counter for a value outside the range, you get no warning or error.
You only get an error if the value goes outside the range in simulation.
If you assign an integer counter from a register with a certain number of bits, the tools will not see a problem if the integer range is too small.
In simulation, the number of bits in the register doesn't matter.
You will only see the error in simulation if the value stored in the register is outside the range.
Unsigned counters does not have these problems.