Junus2012
Advanced Member level 5
Hello,
I am using the 0.35 µm CMOS technology,
I designed for my purposes some simple clock generator circuit using the inverter ring oscillator. The circuit generates high clock frequency signal (120 MHz),
I am wondering if chip pad can respond to this frequency or not, where can I find such information.
Upon your experience, what is the maximum clock frequency I can safely use to drive an output pin.
For sure I need to design buffer stage to drive the pad, how much I should consider the PAD load capacitor?
Thank you
Best Regards
I am using the 0.35 µm CMOS technology,
I designed for my purposes some simple clock generator circuit using the inverter ring oscillator. The circuit generates high clock frequency signal (120 MHz),
I am wondering if chip pad can respond to this frequency or not, where can I find such information.
Upon your experience, what is the maximum clock frequency I can safely use to drive an output pin.
For sure I need to design buffer stage to drive the pad, how much I should consider the PAD load capacitor?
Thank you
Best Regards