Maximum frequency and Spartan3

[borntofight22]

Hi!

I'm new to FPGAs. I have this board:
**broken link removed**
Someone know what the maximum frequency may accept (Spartan) one of the pin:

# ==== 6-pin header J1 ====
# These four connections are shared with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL  ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL  ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL ;
# ==== 6-pin header J2 ====
# These four connections are shared with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL  ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL  ;

If I will use Global clock buffer Spartan will accept 300 MHz, but
I have a frequency of 120MHz and I want to use "normal" pin input. It will not destroy board??

Please help me..

 

[svhb]

I saw in the datasheet of spartan3, that the TIOPICK is a bit smaller than 2ns. So signals above this frequency will probably not propagate through the I/O-block into the logic array.
This means that (in theory) a maximum of 500MHz can be used (without taking further routing delays, logic delays, ... into account).

The power dissipation of an fpga is mainly determined by the clock frequency the flip-flops toggle on (and so also the rest of the internal logic). A few inputs toggling at 120Mc will not blow the component.

Stefaan