Maximum clock frequency

[shaiko]

When an FPGA manufacturer states that his device can run at a maximum frequency X...what does it mean?

For example, surely the device can't handle a full floating point division operation at that speed...so what does that speed relate to?

 

[TrickyDicky]

It is the frequency based on the shortest register -> register dely in the device. Like you have noted, this is very unrealistic. At best you may acheive only 80% of this max frequency.

 

[shaiko]

At best you may acheive only 80% of this max frequency.

And this is without any computation between the registers...correct?
Add a simple XOR operation and the speed will drop accordingly.

 

[TrickyDicky]

In a real design your max frequency is determined by the worst case path, so there will always be some "computation" as you put it between registers. For max frequency you need to ensue you have no more than 1 LUT between registers (which can have several gates) and the registers are not on opposite sides of the chip. But its not usually the routing through LUTs thats the problem. The DSPs and RAMs are in fixed locations, unlike logic, and often the timing problems occur either into or out of them. So often you need extra pipeline registers before or after them just to improve the routing in the design.