maximum achievable resource utilization in Virtex-4 FPGA ?

[gongdori]

Hi all,

I've used Virtex-4 SX35 before. When I used 80%of LUT and 75% of register, it became unroute-able. I've used three BUFGs and a few BUFIOs.
In case of V4-Fx100, the maximum I could reach was less than those numbers, and I used more BUFGs.

I know it really depends on design, but I wonder what the realistic maximum utilization we can get.
Can you guys share how much you have filled up?

Gongdori

 

[TrickyDicky]

Ive seen usage in the 90%+. At that point it has to work really hard to route it. It really depends on design.