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max_transition violation in my design

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subhash_chevella

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hello all,

After synthesis, my desing has no violations in Timing. But I am getting max_transition violation? Can any one help how to fix this violation?


Required Actual Slack
oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PORT : oTmrTopWdRst 0.24 0.36 -0.12 (VIOLATED)
PIN : U17/ZN 0.24 0.36 -0.12 (VIOLATED)


I tried with compile -inc -only_desgin_rule also. No improvement.

thanks & regards,
Subhash
 

rca

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To remind, the liberty time table have on axis, transition & capacitance. The trans (or cap) violation only indicates your are outside this table, and so you need to be aware the tool do some extra-interpolation to estimate the timing. And if the violation is "huge", you could know if the interpolation is optimistic or pessimitic.
 

subhash_chevella

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hi shitansh,
I am using Design Compiler.

Hello rca,
Can you explain it clearly? what is "table" indicates here..?

regards,
Subhash
 

shitansh

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In RTL compiler there is one command which sets high priority for DRC rules for synthesis.

I think same kind of command will be there in DC too, In one word you have to run synthesis with DRC check as high priority.

HTH,
Shitansh Vaghela
 

rca

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the liberty file gives you this:
cell rise in xxx ns depending of index_1 and index_2:

index_1 is transition (see below) and the cell is caracterize for a transition up to 1.136ns.
index_1 is cap (see below) and the cell is caracterise for an output cap up to 0.03477pF

cell_rise (delay_template_7x7_0) {
index_1 ("0.0057, 0.0237, 0.0595, 0.1313, 0.2748, 0.5618, 1.136");
index_2 ("0.00055, 0.00109, 0.00218, 0.00435, 0.0087, 0.01739, 0.03477");
values ( \
"0.07133, 0.08024, 0.0966, 0.1273, 0.1876, 0.3075, 0.5468", \
"0.07788, 0.08678, 0.1032, 0.134, 0.1943, 0.3143, 0.554", \
"0.08936, 0.0983, 0.1147, 0.1455, 0.2061, 0.3259, 0.5657", \
"0.1094, 0.1184, 0.1348, 0.1657, 0.2262, 0.3463, 0.5856", \
"0.1382, 0.1478, 0.1646, 0.1958, 0.2562, 0.3763, 0.616", \
"0.1718, 0.1828, 0.2008, 0.2323, 0.2928, 0.413, 0.6523", \
"0.2014, 0.2153, 0.237, 0.2709, 0.3315, 0.451, 0.6911" \
);
}

with delay_template_7x7_0 => table 7 by 7 with variable_1 (=index_1) is transition and variable_2(index_2) is cap

lu_table_template (delay_template_7x7_0) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007");
index_2 ("0.0001, 0.0002, 0.0003, 0.0004, 0.0005, 0.0006, 0.0007");
}

this example come from a 65nm std cell library
 

pavanks

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I have not worked in frontend. But if u have less number of design rule violations, then can't u fix these manually ?
 

jeevan.life

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the transition time is higher than the threshold (slew). You can increase the drive strength or add buffers.
 

SSTA

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Hi Guys,

Just a quick question. Why max transiton violations are much higher in fast corner compared to the slow corner?
How to explain this?
 

dftrtl

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It all depends on what options you have used to do DC synthesis. Tradeoff between timing and area.
 

SSTA

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It all depends on what options you have used to do DC synthesis. Tradeoff between timing and area.

Sorry, but... it is not clear to me, why with the same constraints I have let's say 500ps transition in slow corner and 1200ps transition in fast corner.

This does not make sence...

I'm not sure how the DC synthesis can have impact on this.. If you have the same load on the output (including interconnect and the next cell input cap), than logically in the slow corner the driving cell should have higher transition than in fast?!
 

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