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Max capacitance violation on macro clk pin

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shragh

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Hi,

After performing CTS with IC Compiler, I get a list of max_capacitance violations on all the clk pins of the macros in my design.

I found out from the logs that the problem is because the clock inverters with higher drive strength (X12, X16, X20) are pruned by the tool (the message says they are pruned due to a gain of *some value*), and hence not used for DRC fixing. As a result, even the clk inverter with the highest drive strength used has an output max capacitance lower than the load capacitance of the macro clk pin.

According to Synopsys documentation, this pruning appears to be out of the user's control. Has anyone faced this issue? If so, is it a good idea to avoid all clk inverters and go with only clk buffers? Or is this maxcap violation something that can be ignored?

Thanks,
 

ThisIsNotSam

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hitting max cap means the tools will not be able to estimate the timing of the cell because the load is outside known parameters. it can be a big issue and lead the tool to wrong results.

no idea why the pruning is happening/
 

shragh

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Quick update on this.

I ran CTS by specifying only clock buffers and no clock inverters in set_clock_tree_references, since during the earlier run, only the inverters were pruned, and not the buffers. While I expected a significant increase in the area of cts-introdduced cells, it wasn't the case. Also, surprisingly, both the worst-case global and local skew are smaller in the tree with only buffers.
More importantly, the maxcap violations are now gone, since the tool uses X16 clk buffers to drive the clk pin of the memory macros.

I have one question regarding this - Earlier, all the clk inverters driving the macro clk pins did not drive any other cells. Now, there are other flip flops in the same sink group as that of the memory macro. I understand that the tool considers phase delay of the macro and balances skew with other flops on the sink group, but I just want to know if it is a good design practice to have other flops being driven by the same clk buffer that drives a memory macro clk pin.

Thanks,
 

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