MAX CAP AND MAX TRANS VIOLATIONS

[sim_333]

max cap violation

CAN ANY ONE EXPLAIN ME ABOUT THE MAX CAP AND MAX TRANS VIOLATIONS THAT OCCUR IN DESIGN AND HOW THEY ARE FIXED BY TOOLS ?

 

[vak]

max trans vs max cap violations

There are different ways to fix max cap and max trans violations. I have listed few of them

1. cloning is done ( if possible )
2. upsizing the cells
3. buffer insertion

 

[sim_333]

slew violations max tran

CAN U SPECIFY THIS WITH AN EXAMPLE OR ANY DOCUMENT RELATED TO THAT

THANKS

 

[sam536]

fix max transition violation

Slew violations (Max trans viol):
maximum transition time for a net is the longest time required for its driving pin to change logic values .

Max cap violations(Load violations)
The maximum capacitance is a pin-level attribute used to define the maximum total capacitive load that an output pin can drive. That is, the pin cannot connect to a net that has a total capacitance (load pin capacitance and interconnect capacitance) greater than or equal to the maximum capacitance defined at the pin.


DC/Back end tools will find the max value from the library. If design is having more than the limit on lib for particular net, its a violation.

How to fix them :
1) Size down the sink
2) buffer the net
3) resize source and lot more ..

Regards,
Sam

 

[sim_333]

max cap max tran

Thanks ,

But i have few more ques , like if u upsize the buffer the driving strength will increase and it can drive a better load ( so max trans fixed on that net ) , so is this heplful in fixing max cap violations also , or tool have to do cloning and decloning for fixing max cap violations.

And how does downsizing of sink helps, means if i dwnsize the sink i ll probably decrase the i/p cap seen by the previous driving pin , so is this fixing max cap violations by doing this.

 

[shiv_emf]

sink max tran

i am clueless ..

what is cloning? upsizing n down sizing og buffer r also used for fixing timing violation .. DRC r also fixed with same??? i am nt clear with this

 

[sim_333]

max_cap violation

Cloning is basically grouping the similar cells together , that r talking with similiar domain , upsizing and down sizing r used for fixing timing violaitons , that i correct , but they can also be used to fix max trans violations as if we upsize a buffer , it can drive a better load and max trans can be fixed , but to fix max cap this is also used but dnt know how ?
Also for fixing max cap violations tool jus divide the load by adding buffer and instead of one buffer driving larger load we have more no of buffers driving that particular load but it is distributed.

 

[sowmya005]

Hi,
I know that buffering will help in solving the slew violations, but there should be limit on number of buffers added. what is the limit? what is the relation between the slew and the number of buffers added?

Please help.
Thanks,
Sowmya.

 

[research235]

according to me you are free to buffer as long as that particular path still meets timing(setup).