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Matrix multiply as a custom IP

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Alex02

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Hello everyone!

I'm using Microblaze to run an application which involves matrix multiplication. At this moment the application is very slow and the code is executed from the DDR SRAM (because the it's too long) and most of the operations are matrix multiply (27 by 27) and matrix inverse (6 by 6). So I'm implementing a custom IP in VHDL for the matrix multiply in order to accelerate the application.

I've attached some custom IPs to the PLB. I've also read that FSL presents a good performace , however I have no experience with this bus. Is it suitable for this case?

Regarding the VHDL design, I think that if I had a group of dual-port ram for every column of the matrix it would be ideal to achieve the matrix multiplication. The problem I see with this approach is related to store data in these memories. So I'm wondering if there is a way to store matrix data efficiently so that it can also allow to access different addresses at the same time.
I have doubts about how to store data in these dual-port memories efficiently (I attached the basic matrix multiply scheme that that I'm doing -> matrix A -1 row, matrix B -1 column ).

Thanks in advance.
Alex
 

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