The code is as below !
I think this is the hardware approach. This code works fine.
Simulation does not mean it's hardware, there are a lot of things you can do that don't work in synthesis. Your "hardware" (I use the term loosely) has no inputs or outputs so will be completely deleted by any synthesis tool.
Using wires to store matrix elements is not hardware you've just made a Verilog software program.
the
reg type is used for storing values. these if written along with
always @ (posedge clk) blocks where all the assignments are done infer Flip-flops or memory (if you code it according to the correct synthesis template).
What you have written will attempt to build a huge combinational circuit that will be very very very very slow. Without a clock and pipelined design techniques this design is worthless for use in any technology (even if it manages to synthesize).
You need to learn digital logic design first before writing Verilog. Can you draw a schematic using gates, Flip-flops, memories that does this matrix operation? Once you do that you write a Verilog hardware description of that circuit.
// this is the bit that matters - everything else just works around shortcomings
// in the language:
The shortcomings aren't in the language the shortcoming is in your understanding that Verilog is a HARWARE DESCRIPTION LANGUAGE, you describe in excruciating detail the Flip-flops, the memories, the gates that make up a digital design. I suppose this is a good reason for teaching HDLs starting with structural code, it's more like hooking up ICs on a PCB than software coding. Trouble is once they introduce if statements students immediately start writing software Verilog/VHDL instead of keeping in mind they are still designing hardware.
- - - Updated - - -
FYI, the first VHDL design I wrote, I drew schematics for the entire design on paper before I started coding anything...
...and the design worked the first time it was download on the FPGA with absolutely NO simulation. Of course I was an EE board designer before I became an FPGA engineer and nearly all the boards I designed worked from their first time powered up.