Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Matching of long transistors

Status
Not open for further replies.

pseudockb

Member level 5
Joined
Aug 4, 2004
Messages
89
Helped
8
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
908
Hi, I am wondering is there any more considerations to be taken into when trying to match very long transistors. For example, I want to use current mirrors to mirror a very small current and the W/L derived is 0.02 so that the transistors are in strong inversion. I chose W to be 1um and L to be 50um. I am also concerned about the long distance that one transistor stretch such that the transistor experiences a large process gradient from one end to the other. Furthermore, the layout is not compact anymore. Any suggestion? Thanks.
 

mpig09

Full Member level 4
Joined
Aug 26, 2005
Messages
227
Helped
8
Reputation
16
Reaction score
2
Trophy points
1,298
Location
Taipei
Activity points
2,786
Dear pseudockb :

How about use several MOS to consist of your or original mos size. ?

eg: W/L=1/50 = five 1/10 mos & serial these mos to like serial R to
get the current that you want value.


mpig09
 

dipswitch

Junior Member level 2
Joined
Jun 7, 2005
Messages
20
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,281
Activity points
1,530
Hi pseudockb,

I would recommend avoiding these lengths, and perhaps doing everything possible design wise to increase the current bias, even if only in one stage. Alternately you could investigate weak-inversion biasing. If you post some details of the design, we might be able to help.

Otherwise if you're stuck with this length, place dummy poly/diffusion on all sides of the devices to improve matching (at cost of area). Also be careful of the models for this transistor; most device engineers do not have a 1/50 device to measure, so all values are extrapolated and therefore less accurate. In addition, watch out for delta-w effects, RSCE (Reverse Short Channel Effect), and narrow width effects.

Regards,
Dipswitch
 

mince

Member level 5
Joined
Feb 19, 2005
Messages
82
Helped
10
Reputation
20
Reaction score
4
Trophy points
1,288
Location
Texas
Activity points
1,894
Definately try to bias in weak inversion. This will increase you W/L ratio so that you can use smaler lengths.
 

pseudockb

Member level 5
Joined
Aug 4, 2004
Messages
89
Helped
8
Reputation
16
Reaction score
1
Trophy points
1,288
Activity points
908
I have read from some papers quoting that current mirrors biased in weak inversion are more proned to mismatch. Furthermore, I cannot increase my current consumption further because of the low power requirement.

I have thought of using the serial connection as mentioned by mpig09 but I am not sure of the mismatch factor. Has anybody tried that before?

Where can I find information on delta-w effects, RSCE (Reverse Short Channel Effect), and narrow width effects? Thanks.
 

phoebe

Newbie level 6
Joined
Jun 3, 2003
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
80
I also feel confused about the current mirror, which one can be controlled better, the normal (like 5u/2u)or the inversion transistor (2u/5u)?which one is more accurate?
 

Karthikeya

Advanced Member level 4
Joined
Jan 9, 2005
Messages
103
Helped
9
Reputation
18
Reaction score
1
Trophy points
1,298
Activity points
989
hi phoebe,
the w/l ratio depends on current that flows through it...w/l <1 is uncommon and also difficult to match in layout. if such a situation occurs operate it in subthreshold region.
w/l ratios close to 1 may be accepted but ratio like 0.02 is highly not recommend.

regards
 

pillar_chen

Member level 3
Joined
Nov 2, 2005
Messages
59
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,288
Activity points
1,682
The ratio is one point, another point is its length and width size, and at same time layout is very important
 

ytass

Junior Member level 1
Joined
Jul 27, 2006
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,416
Hi there,

I'm also doing an ota design with ultra low currents (400nA), and need some transistors with W/L = 1/50 to get my Veff = 0.2V. Does everyone recommend that I operate these current mirrors in subthreshold? But surely the device mismatch won't be good?

Are there good long-length mosfet matching techniques?

Thanks for your help.
 

rfsystem

Advanced Member level 3
Joined
Feb 25, 2002
Messages
914
Helped
149
Reputation
294
Reaction score
38
Trophy points
1,308
Location
Germany
Activity points
9,548
MOS mismatches have two factors

1. Threshold voltage mismatch
2. Mobility mismatch

If you plot the mismatch of the same area device over different VDSATs you get the best matching near maximum VDSAT=VDD-VTH. At lower VDSAT, or below the subthreshold transition point the current mismatch does not change any more. The device operate similar to a bipolar with a bad matching. The matching is then only defined by VTH mismatch.

I think the expression is

sigID/ID=sigVTH(W,L)/(m*VT)
 

ytass

Junior Member level 1
Joined
Jul 27, 2006
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,416
Hi rfsystem,

Thanks for your reply, although I don't think you addressed my question at all.

What I am asking is, are there good layout techniques for long length transistors, in particular, are there ways to layout long length current mirrors?
The only reference I have for long length transistors is the layout given in Baker's book (CMOS Circuit Design, Layout and Simulation, 2nd edition, p120).

Any help would be greatly appreciated.
Thanks.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top