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If you are talking about hand calculating the offset then you need the matching coefficients which are generally measured from silicon. These coefficients can be scaled inversely with the square root of the area of a device to calculate the matching between two areas in 2 dimensions. I am not sure what you mean with 3 dimensional matching? Do you mean like MOS gate area and also the tox thickness matching? If that then normally depths and thicknesses are very tightly controlled in a process, so it will not be significant if your devices are close to each other. And anyway when you use the matching coefficient from silicon in a way it would include the effect of thickness variation also if any.