Map design to Logic Elements or DSPs?

[eruisi]

I have a filter design in verilog and I want to compile it to Altera Stratix.

In Quartus II, I have an option that can balance mapping to Logic Elements or DSPs. If I choose LEs, no DSP will be used. All calculations are implmented in logics. If I choose DSP, most calculations will be mapped to DSP blocks.

However, I found that the power estimation for DSP implementation is higher than the LE version, which is different from my intuition. I remember that arithmetic operation are preferred to implement in DSP blocks to save interconnection and power but I just get the opposite results.

I use PowerPlay to estimate the power.

 

[rsrinivas]

wat's ur data format??

 

[eruisi]

You mean codes? In Verilog.

wat's ur data format??

 

[alt007]

HIi,
It is possible bz our logic may simple ,so the LE IS USED LESS and u get less power consumption but when DSP implementation is there a fixed amount of le will be used that is causing more power consumption.

Regrads
alt007

 

[eruisi]

This makes sense.

There is one example
For the balance of LE: 2586 LEs, 0 9-bit DSPs, Power 44.33mW
For the balance of DSP: 2067 LEs, 20 9-bit DSPs, Power 46.40mW


What's that fix amount of LEs used for?

HIi,
It is possible bz our logic may simple ,so the LE IS USED LESS and u get less power consumption but when DSP implementation is there a fixed amount of le will be used that is causing more power consumption.

Regrads
alt007

 

[rsrinivas]

say have 12 bit data
but ur mul's and add's(DSP's) are 18 bit(say)
so the data be zero padded,and as mul's are the one's which constitute for most of the power in any circuit it may be increasing ur power consumption.
check the mul's width in the DSP slice u r using and change ur code to match the width of the muls' and repeat the procedure.pls do let us know the results.