Mar 24, 2009 #1 M mr_byte31 Full Member level 5 Joined Oct 19, 2005 Messages 295 Helped 10 Reputation 20 Reaction score 8 Trophy points 1,298 Activity points 3,241 hi all i am making an FIR filter for practicing VHDL what i need is : work with fixed point like addition and mul i use FPGA advantage 7.2 and i have xilinx 10.1 also any suggestions??
hi all i am making an FIR filter for practicing VHDL what i need is : work with fixed point like addition and mul i use FPGA advantage 7.2 and i have xilinx 10.1 also any suggestions??
Jul 11, 2009 #2 G goli61 Newbie level 2 Joined Jul 10, 2009 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,292 vhdl fixed point Hello, I have the same problem, Did you solve your problem ?
Jul 11, 2009 #3 M mr_byte31 Full Member level 5 Joined Oct 19, 2005 Messages 295 Helped 10 Reputation 20 Reaction score 8 Trophy points 1,298 Activity points 3,241 fixed-point vhdl not yet
Jul 13, 2009 #4 L lmtg Member level 3 Joined Jan 25, 2009 Messages 65 Helped 4 Reputation 8 Reaction score 2 Trophy points 1,288 Activity points 1,686 vhdl fixpoint Suggestions concerning what??
Jul 14, 2009 #5 H haneet Full Member level 3 Joined Nov 7, 2006 Messages 160 Helped 14 Reputation 28 Reaction score 1 Trophy points 1,298 Activity points 2,219 noise cancellation +digital filters +vhdl code cld u tell us wht exactly are u expecting?? ur questn is not clear.... haneet
noise cancellation +digital filters +vhdl code cld u tell us wht exactly are u expecting?? ur questn is not clear.... haneet