making a HV device in LV process ?

[Btrend]

Is it possible to make a HV (High Voltage) device in LV (Low voltage) process with only extra 2 ~ 4 masks. ?

I heard that some company made such HV device in house to cost down their chip both in area and mask cost !

Is there any reference ?

thanks in advance

 

[leo_o2]

Yes, a easier way is HV extension MOS. Need a mask for drain well and a mask for thick gate oxide.

 

[mdcui]

yes, by growing the oxide layer thicker for the HV transistors and adjust the doping density for source/drain area, you can have a different type of HV transistors integrited in the same process, we use this techniq a lot.

 

[jttzeng]

What is your definition of the HV devic ? "To make the HV device in LV process " does it mean only LV oxide allowed ?
If only drain side HV device is needed, LV process with LV oxide could have such HV device through the drain side layout and doping engineer (may be logic process compatible, no needs for extra mask).
But if your design need full range HV swing for D,S and Gate, you have to go for the HV process for dual gate oxide.