Making a function FOR A SUB PROGRAM

[chat]

i have to modify a sub program by putting it inside a function , so whenever that function is called the program inside the function executes and the result of that program should be given as input to the main program..?

HOW TO DO THAT...?

 

[TrickyDicky]

That sounds like software programming to me.

to write a function:

function my_function( a : integer ) return integer is
begin
return a + 7;
end function;

and to call it:

some_integer <= my_functions(input);

 

[vipinlal]

A function can only contain combinatorial logic. Does your subprogram combinatorial?

I hope you are talking about vhdl here.

 

[chat]

yup.. in vhdl i have made a subprogram using a for loop .. i want to make it inside a function so that i can call it whenever i require in the main program.

 

[vipinlal]

Share your sub program here. I think you just need to copy paste the code inside the function and change the function declaration accordingly.

 

[chat]

this the program..


entity calling is
port( ParseFinalMt:in std_logic_vector(335 downto 0 );
test_endstm:inout integer;
test_else:inout integer;
test_else2:inout integer;
test_else3:inout integer;
in_test2:inout integer;
in_test3:inout integer);
end calling;

architecture Behavioral of calling is
type arrparse1 is array (6 downto 0) of integer;

begin
process(ParseFinalMt)
variable ap_rem:arrparse1;
variable size_store,hash_count,j,new_s1,test_parse,u:integer;
variable a7_parse:std_logic_vector(7 downto 0);

begin
for u in 8 downto 0 loop ----------------i want to use while loop


if test_parse/=10 then
if (test_parse>=171 and test_parse<=181) then


l1: while hash_count>=1 loop
if test_parse/=35 then
New_s1:=New_s1-8;
else

hash_count:=hash_count-1;
test_else<=hash_count;

for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;

end loop;
if hash_count=1 then

test_parse:=conv_integer(a7_parse);
ap_rem(size_store):=test_parse;
in_test2<= ap_rem(size_store);
test_else2<=hash_count;
size_store:=size_store-1;
else
if hash_count<1 then
test_parse:=conv_integer(a7_parse);
ap_rem(size_store):=test_parse;
in_test3<= ap_rem(size_store);
test_else3<=hash_count;
size_store:=size_store-1;
end if ;
end if ;

end if;
-- exit when hash_count<=1 ;
------------------------------------------------------------------------------------------


for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;
end loop;
test_parse:=conv_integer(a7_parse);
exit l1 when hash_count=0;
end loop l1;

while test_parse/=10 loop

for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;
end loop;
test_parse:=conv_integer(a7_parse);

end loop ;
--while test_endstm<=test_parse;
end if;
else
New_s1:=New_s1-8;

end if;

--exit;
for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;
end loop;
test_parse:=conv_integer(a7_parse);

for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;
end loop;
test_parse:=conv_integer(a7_parse);


if test_parse=126 then
test_parse:=conv_integer(a7_parse);
test_endstm<=test_parse;

exit;
end if ;

end loop ;
end process;
end Behavioral;

---------- Post added at 14:22 ---------- Previous post was at 14:07 ----------

can u let me know the solution to this ?

 

[vipinlal]

I didnt go through the code, but if this is your subprogram then you cant use it inside a function. You have to instantiate it (port map it). Google for "Instantiation of components in vhdl" .

 

[chat]

ok.. can i use array and function after architecture 1 after another ?

 

[vipinlal]

You can use the logic alone inside the function.

 

[chat]

can u let m me know(syntax) how an array and function can be declared at the architectural level for a small program

 

[vipinlal]

See how a function is defined in the architectural part of the code here:
VHDL coding tips and tricks: Recursive functions in VHDL

Note that its just an example. The code logic is not related with what you want here.

 

[chat]

please let me know the errors in this program..


entity phrase is
port( ParseFinalMt:in std_logic_vector(35 downto 0 );
clk:in std_logic_vector);
end phrase;

architecture Behavioral of phrase is

function latch (ParseFinalMt : std_logic_vector) return std_logic_vector is
variable output : std_logic_vector;
variable new_s1:integer;
variable a7_parse:std_logic_vector(7 downto 0);
variable j:integer;

begin

for j in 7 downto 0 loop
a7_parse(j):=ParseFinalMt(New_s1);
New_s1:=New_s1-1;
end loop;
output <= new_s1;
return output;
end latch;

begin
process (clk)
begin

output <= latch(ParseFinalMt);
end process;
end Behavioral;

 

[TrickyDicky]

variables have to be assigned using the := rather than <= (you've assigned output in the function with <=)

There is no output declared in your entity.

New_s1 isnt assigned an initial value, so it will start at -2billion.

And the final problem - the function doesnt do anything. It just returns the same thing every time its called.

 

[chat]

can u suggest a good program (or modify it !!) for me to better understand functions ?

 

[permute]

as always:
you might consider using x(m downto n) := y(j downto k); -- this structure can get rid of most of the for loops as well as what I'm assuming is the intent of the functions.

Also, most synthesizers don't like while loops, nor do most hardware developers. synthesis has to unroll all loops to create the hardware that can perform them. While loops might never end (for some inputs), so the synthesizer has issues. even when the tools find a solution, it might not be very good. For simulation you are ok though.

 

[chat]

as i am a newbie to vhdl... can u write the the proper code for the above program..

---------- Post added at 11:40 ---------- Previous post was at 11:39 ----------

which can be executed ?

---------- Post added at 12:04 ---------- Previous post was at 11:40 ----------

as i am a newbie to vhdl... can u write the the proper code for the above program..

---------- Post added at 11:40 ---------- Previous post was at 11:39 ----------

which can be executed ?

---------- Post added at 12:05 ---------- Previous post was at 12:04 ----------

as i am a newbie to vhdl... can u write the the proper code for the above program..

---------- Post added at 11:40 ---------- Previous post was at 11:39 ----------

which can be executed ?

---------- Post added at 12:05 ---------- Previous post was at 12:05 ----------

as i am a newbie to vhdl... can u write the the proper code for the above program..

---------- Post added at 11:40 ---------- Previous post was at 11:39 ----------

which can be executed ?

 

[mrflibble]

Well, the best method to un-n00b yourself is to do the actual writing of the proper code. So what have you written for the above program yourself, and what specifically is not working?

 

[FvM]

I found, that the original program in post #6 apparently has unrestricted loops and isn't synthesizable. So I don't see any use in changing it to a different code style without clarifying it's purpose.

P.S.: Also the original code has uninitialized variables. So it can't work in a VHDL simulator either.

 

[TrickyDicky]

The biggest problem is integers on inout ports. Thats a complete non-starter, whether you simulate or try and synthesise